Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
66 words
A bus driver circuit (200) having input means adapted to receive data input signals, and an output node (238) connected to a data transfer bus adapted to transfer data in the form of first and second logic level signals, characterized by clamping means (228,242) adapted to prevent the voltage on said data transfer bus from transcending the range defined by said first and second logic levels.
Claim 2
Dependent Claim
52 words
A bus driver circuit according to claim 1, characterized by a first transistor (228) connected to a first voltage source defining said first logic level and to said data transfer bus, a second transistor (242) connected to a second voltage source defining said second logic level and to said data transfer bus.
Claim 3
Dependent Claim
90 words
A bus driver circuit according to claim 2, characterized in that said first transistor (228) is adapted to act as a clamping diode when said data transfer bus is at said second logic level to pull the voltage on said data transfer bus up to said second logic level and in that said second transistor (242) is adapted to act as a clamping diode when said data transfer bus is at said first logic level to pull the voltage on said data transfer bus down to said first voltage level.
Claim 4
Dependent Claim
46 words
A bus driver circuit according to claim 3, characterized by a third transistor (226) connected between said first voltage source and the gate of said first transistor, and a fourth transistor (240) connected between said output node (238) and the gate of said second transistor (242).
Claim 5
Dependent Claim
80 words
A bus driver circuit according to claim 4, characterized by a fifth transistor (216) connected between a third voltage source and the gate of said first transistor (228) and a sixth transistor (230) connected between said third voltage source and the gate of said second transistor (242) and in that said input means is coupled to the gates of said fourth and sixth transistors (240,230) and via inverter means (210,212) to the gates of said third and fifth transistors (228,216).
Claim 6
Dependent Claim
32 words
A bus driver circuit according to claim 5, characterized in that the voltage value of said third voltage source is greater in magnitude than the voltage value of said first voltage source.
Claim 7
Dependent Claim
45 words
A bus driver circuit according to any one of the preceding claims, characterized by disabling means (218,220,232,236) adapted to disable said bus driver circuit from providing said first and second logic level signals on said data transfer bus, while maintaining said clamping means (228,242) operative.