EP0486295A2 — Semiconductor memory device with redundant circuit

Claim 1

Independent Claim 489 words

A semiconductor memory device fabricated on a single semiconductor memory chip (11), comprising: a) a regular memory cell array (11) having a plurality of regular memory cells (M11 to Mmn) arranged in rows and columns and respectively storing data bits; b) a plurality of first power voltage lines (PW1 to PWa) assoicated with said rows of said memory cells for distributing a first power voltage level (Vcc); c) a plurality of second power voltage lines (GD1 to GDa) assoicated with said rows of said memory cells for distributing a second power voltage level different from said first power voltage level (GND); d) a plurality of regular word lines (WL1 to WLm) respectively asscoated with said rows of said regular memory cells, and selectively driven to an active level for allowing data bits to be read out from a row of said regular memory cells; e) a plurality of redundant memory cells (RM11 to RM2n) respectively storing data bits, and coupled with redundant word lines (RWL1/ RWL2); f) a redundant word line driving unit (18) selectively driving said redundant word lines to said active level for allowing data bits to be read out from redundant memory cells selected from said plurality of redundant memory cells when one of said plurlaity of regular memory cells to be accessed is defective; g) a row address decoding means (15/16) having g-1) a plurality of regular driver circuits (151 to 15n) respectively associated with said word lines and coupled in parallel between a first source line (Vcc) of said active level and a second source line (GND) of an inactive level for selectively coupling said assoicated regular word lines with said first and second souce lines, and g-2) a plurality of activation circuits (151a) assoicated with said plurality of regular word lines and responsive to row address bits for allowing said regular driver circuits to selectively couple said asoicated word lines with said first and seocnd source lines; and h) a plurality of bit line pairs (BL1 to BLn) associated with said regular memory cell array and said redundant memry cell array, and respectively coupled with said columns of said regular memory cells and said redundant memory cells for propagating said data bits to a column selector unit (14), characterized in that said row address decoding means further has g-3) a plurality of first cut-off means (151d) associated with said plurality of activation circuits and with said first power voltage lines, and coupled between a main power supply line (MPS) and said associated first power voltage lines, said plurality of first cut-off means being selectively broken for isolating said assoicated first power voltage lines from said main power supply line when one of said regular memory cells in said associated rows is defective, said plurality of activation circuits causing the assoicated regular driver circuits to forcibly shift said assoicated regular word lines to said inactive level when said assocaited first cut-off means are broken.

Claim 2

Dependent Claim 489 words

A semiconductor memory device fabricated on a single semiconductor memory chip (11), comprising: a) a regular memory cell array (11) having a plurality of regular memory cells (M11 to Mmn) arranged in rows and columns and respectively storing data bits; b) a plurality of first power voltage lines (PW1 to PWa) assoicated with said rows of said memory cells for distributing a first power voltage level (Vcc); c) a plurality of second power voltage lines (GD1 to GDa) assoicated with said rows of said memory cells for distributing a second power voltage level different from said first power voltage level (GND); d) a plurality of regular word lines (WL1 to WLm) respectively asscoated with said rows of said regular memory cells, and selectively driven to an active level for allowing data bits to be read out from a row of said regular memory cells; e) a plurality of redundant memory cells (RM11 to RM2n) respectively storing data bits, and coupled with redundant word lines (RWL1/ RWL2); f) a redundant word line driving unit (18) selectively driving said redundant word lines to said active level for allowing data bits to be read out from redundant memory cells selected from said plurality of redundant memory cells when one of said plurlaity of regular memory cells to be accessed is defective; g) a row address decoding means (15/16) having g-1) a plurality of regular driver circuits (151 to 15n) respectively associated with said word lines and coupled in parallel between a first source line (Vcc) of said active level and a second source line (GND) of an inactive level for selectively coupling said assoicated regular word lines with said first and second souce lines, and g-2) a plurality of activation circuits (151a) assoicated with said plurality of regular word lines and responsive to row address bits for allowing said regular driver circuits to selectively couple said asoicated word lines with said first and seocnd source lines; and h) a plurality of bit line pairs (BL1 to BLn) associated with said regular memory cell array and said redundant memry cell array, and respectively coupled with said columns of said regular memory cells and said redundant memory cells for propagating said data bits to a column selector unit (14), characterized in that said row address decoding means further has g-3) a plurality of first cut-off means (151d) associated with said plurality of activation circuits and with said first power voltage lines, and coupled between a main power supply line (MPS) and said associated first power voltage lines, said plurality of first cut-off means being selectively broken for isolating said assoicated first power voltage lines from said main power supply line when one of said regular memory cells in said associated rows is defective, said plurality of activation circuits causing the assoicated regular driver circuits to forcibly shift said assoicated regular word lines to said inactive level when said assocaited first cut-off means are broken.

Claim 3

Dependent Claim 139 words

A semiconductor memory device as set forth in claim 1, in which each of said regular memory cells and said redundant memory cells comprises a series combination of a first resistor (R1) and a first transistor (QN1) of a first channel conductivity type coupled between said assocaited first and second power voltage lines, a series combination of a second resistor (R2) and a second transistor (QN2) of said first channel conductivity type coupled between said assoicated first and second power voltage lines, and a couple of third transistors (QN3/QN4) coupled between the drain nodes of said first and second transistors and said asoicated bit line pair and gated by said assoicated regular word line or by said assoicated redundant word line, said first and second transistors being gated by said drain nodes of said second and first transistors, respectively.

Claim 4

Dependent Claim 151 words

A semiconductor memory device as set foth in claim 2, in which each of said activation circuits comprises a plurality of fourth transistors (QP41 to QP43) of a second channel conductivity type and a fifth transistor (QP40) of said second channel conductivity type coupled in parallel between a third source line (Vcc) of power voltage level and a control line (151e) and respectively gated by row address bits selected from said row address bits, and a plurality of sixth transistors (QN44 to QN46) of said first channel conductivity type and a seventh transistor (QN47) of said first channel conductivity type coupled in series between said control line and a fourth source line (GND) of power voltage level different from said third source line and respectively gated by said row address bits selected from said row address bits, said fifth and seventh transistors being gated by said associated first power voltage line.

Claim 5

Dependent Claim 133 words

A semiconductor memory device as set forth in claim 3, in which each of said regular driving circuits comprises a series combination of an eighth transistor (QP49) of said second channel conductivity type and a ninth transistor (QP50) of said second channel conductivity type coupled between said first source line and said associated regular word line, a parallel combination of and a tenth transistor (QN50) of said first channel conductivity type and an eleventh transistor (QN51) of said first channel conductivity type coupled between said associated regular word line and said second source line, said eighth and eleventh transistors being gated by a row address bit (AO) selected from said row address bits and the complementary row address bit thereof (CAO), respectively, said ninth and tenth transistors being gated by said control line.

Claim 6

Dependent Claim 54 words

A semiconductor memory device as set forth in claim 4, in which each of said first cut-off means comprises a first fuse element (151f) coupled between said main power line and said associated first power voltage line, and a third resistor(151g) coupled between said associated first powervoltage line and said second power voltage line.

Claim 7

Dependent Claim 24 words

A semiconductor memory device as set forth in claim 5, in which said third resistor is as large in resistance as about 10 giga-ohms.

Claim 8

Dependent Claim 243 words

A semiconductor memory device as set forth in claim 2, in which said semiconductor memory device further comprises i) a charging unit (30) responsive to a control signal (BL) for coupling said plurality of bit line pairs with a fifth source line (Vcc) of power voltage and for equalizing component bit lines of each of said plurality of bit line pairs, j) a redundant bit line pair (RBL) coupled between said charging unit and said column selecting unit, k) additional regular memory cells (RC1/RCm) coupled with said redundant bit line pair and gated by said regular word lines, respectively, 1) additional redundant memory cells (RCr/RCs) coupled with said redundant bit lines and gated by said redundant word lines, respectively, and m) a column address decoding unit (31) responsive to column address bits for allowing said column selecting unit to couple one of said plurality of bit line pairs with a data bus (DS) in so far as said plurality of bit line pairs are used, said column selecting unit being further operative to couple said redundant bit line pair with said data bus when one of said plurality of bit line pairs replaced with said redundant bit line pair is designated by said column address bits, said column address decoding unit being further operative to isolate said data bus from said plurality of bit line pairs when said one of said plurality of bit line pairs is designated by said column address bits.

Claim 9

Dependent Claim 171 words

A semiconductor memory device as set forth in claim 7, in which said column address decoding unit comprises m-1) a plurality of driver circuits (311 to 31 n) respectively associated with said plurality of bit line pairs, and responsive to said column address bits for allowing said column selecting unit to couple one of said bit line pairs with said data bus, m-2) a plurality offirstcharging circuits (321 to 32n) respectively supplying current from said fifth source line to said bit line pairs, m-3) a second charging circuit supplying current from said fifth source line to said redundant bit line pair, and m-4) a second cut-off means (34/35) operative of cut off said one of said plurality of bit line pairs from said current when said one of said plurality of bit line pairs is replaced with said redundant bit line pair and to cause one of said second driver circuits associated with said one of said plurality of bit line pairs to be not responsive to said column address bits.

Claim 10

Dependent Claim 143 words

A semiconductor memory device as set forth in claim 8, in which each of said first charging circuits is implemented by a pair of twelfth transistors (QP64/QP65) of a second channel conductivity type opposite to said first channel conductivity type coupled between said fifth source line and one of said plurality of bit line pairs, and in which said second cut-off means has a second fuse element (34) associated with said each of said first charging circuits and coupled between the gate electrodes of said twelfth transistors and a sixth source line (GND) of power voltage level different from said fifth source line, and a fourth resistor (35) coupled between said fifth source line and said gate electrodes of said twelfth transistors, the voltage level at said gate electrodes of said twelfth transistors enabling or disenabling one of said plurality of driver circuits.

Claim 11

Dependent Claim 45 words

A semiconductor memory device as set forth in claim 9, in which said one of said driver circuits associated with said second fuse element and said fourth resistor is provided for bit line pairs (BL1 to BL8) selected from said plurality of bit line pairs.

Claim 12

Dependent Claim 73 words

A semiconductor memory device having regular memory cells (M11 - Mmn; RC1 - RCm) and redundant memory cells (RM11 - RM2n; RCr - RCs), and means (16, 17, 18, 21) for controlling the cells such as to functionally replace the defective regular memory cells by redundant memory cells, characterised by means (151f; 34) for interrupting the power supply to those regular cells the function of which is being replaced by redundant memory cells.

Claim 13

Dependent Claim 73 words

A semiconductor memory device having regular memory cells (M11 - Mmn; RC1 - RCm) and redundant memory cells (RM11 - RM2n; RCr - RCs), and means (16, 17, 18, 21) for controlling the cells such as to functionally replace the defective regular memory cells by redundant memory cells, characterised by means (151f; 34) for interrupting the power supply to those regular cells the function of which is being replaced by redundant memory cells.

Semiconductor memory device with redundant circuit

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