EP0486304A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Initialising computer systems
Assignee: Fujitsu Ltd
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Filing: 1991-11-14
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Granted: —
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Expires: 2011-11-14
Abstract
Abstract An initialisation system is disclosed for a close-coupled multiprocessor system which in- dudes a plurality of processors (P1 to P4) and one main memory (2) connected to the processors through a system bus (SB). The initialisation system (31 to 34) is connected to the processors (P1 to P4) through the system bus, and includes : a first storage (31) for storing identification (ID) codes corresponding respectively to the processors, one of the ID codes designating a master processor and other ID codes having a priority for designating the next master processor ; a second storage (32) for storing a program to initialise the system and a program to supervise an initialisation time; a first information unit (33) for indicating the start of operation of the processors; and a second information unit (34) for indicating the completion of initialisation of the master processor. Such an initialisation system can permit the main system to be initialised properly even if the first designated master processor fails to complete the initialisation operation successfully.
Inventors
- 👤 Kazuhiko c/o PFU Limited Ikeda
- 👤 Satoru c/o Fujitsu Limited Sakai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 07:58
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/177
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
149 words
Data processing apparatus including a plurality of individual processors (P1 to P4) and also including initialisation means (3) connected to the said processors and operative in response to a predetermined event to cause a preselected first one (P1) of the said individual processors to commence an initialisation operation for initialising the apparatus; characterised in that the said initialisation means include processor designating means (31) operable to designate a preselected second processor (P2) of the said plurality, and in that at least one of the said processors (P2 to P4) other than the said first one (P1) is operable to determine whether or not the said first one of the processors completes the said initialisation operation successfully within a predetermined time interval and, if not, to cooperate with the said processor designating means (31) so as to cause the said preselected second processor (P2) to commence the said initialisation operation.
Claim 2
Dependent Claim
149 words
Data processing apparatus including a plurality of individual processors (P1 to P4) and also including initialisation means (3) connected to the said processors and operative in response to a predetermined event to cause a preselected first one (P1) of the said individual processors to commence an initialisation operation for initialising the apparatus; characterised in that the said initialisation means include processor designating means (31) operable to designate a preselected second processor (P2) of the said plurality, and in that at least one of the said processors (P2 to P4) other than the said first one (P1) is operable to determine whether or not the said first one of the processors completes the said initialisation operation successfully within a predetermined time interval and, if not, to cooperate with the said processor designating means (31) so as to cause the said preselected second processor (P2) to commence the said initialisation operation.
Claim 3
Dependent Claim
130 words
An initialization system for a close-coupled multiprocessor system which includes a plurality of processors and one main memory connected to the processors through a system bus, and the initialization system connected to the processors through the system bus, the initialization system comprising: a first storage (31) for storing identification (ID) codes each corresponding to the processor, one of the ID codes being designated as a master processor, and other ID codes having a priority for designating the next master processor; a second storage (32) for storing a program to initialize the system and a program to supervise an initialization time; first information means (33) for informing of the start of operation of the processors; and second information means (34) for informing of the completion of initialization of the master processor.
Claim 4
Dependent Claim
130 words
An initialization system for a close-coupled multiprocessor system which includes a plurality of processors and one main memory connected to the processors through a system bus, and the initialization system connected to the processors through the system bus, the initialization system comprising: a first storage (31) for storing identification (ID) codes each corresponding to the processor, one of the ID codes being designated as a master processor, and other ID codes having a priority for designating the next master processor; a second storage (32) for storing a program to initialize the system and a program to supervise an initialization time; first information means (33) for informing of the start of operation of the processors; and second information means (34) for informing of the completion of initialization of the master processor.
Claim 5
Dependent Claim
54 words
An initialization system as claimed in claim 2 wherein, the first storage (31) comprises a non-volatile memory for storing ID codes each corresponding to the ID code of the processor, one of the ID codes being designated as the master processor and other ID codes having a priority to designate the next master processor.
Claim 6
Dependent Claim
42 words
An initialization system as claimed in claim 2 or 3 wherein the second storage (32) comprises a read only memory (ROM) for storing an initialization program to initialize the system and a supervisory program for supervising initialization time of the master processor.
Claim 7
Dependent Claim
43 words
An initialization system as claimed in claim 2, or 4 wherein the first information means (33) comprises registers (R1 to R4) each corresponding to the processor (P1 to P4), and each register storing a flag indicating the start of operation of all processors.
Claim 8
Dependent Claim
37 words
An initialisation system as claimed in any one of claims 2 to 5, wherein the second information means (34) comprises a register (R5), and the register storing a flag indicating completion of initialization by the master processor.
Claim 9
Dependent Claim
75 words
An initialization system as claimed in claim 6, wherein the completion flag is turned ON in the register (R5) when the initialization operation is normally completed by the master processor (P1), other processors (P2 to P4) supervise this completion flag, and when the completion flag is not turned ON after a predetermined initialization time, one of the other processors having the highest priority becomes the next master processor instead of the first master processor (P1).
References Cited (Backward Citations)
No citation records indexed.
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