Patent US4248193A successfully refreshed from Google Patents.
Patent US2304866A successfully refreshed from Google Patents.
EP0486829A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device and semiconductor device packaging system
Assignee: Seiko Epson Corp
•
Filing: 1991-10-22
•
Granted: —
•
Expires: 2011-10-22
Abstract
Abstract A package (1) comprising a first semiconductor chip (100) with pads for wire bonding and contacts for chip-to-chip interconnection, and a second semiconductor chip (200) also with contacts for chip-to-chip interconnection is mounted on a substrate (4) with a printed circuit (6). The first and second chips are coupled together via respective contacts. Chip-to-chip interconnections can be made by heat hardened silver pastel by anisotropic conductive material (9) or by a tape carrier having printed wires (9') supported by flexible film (8a). The two chips together are tightly-coupled pair having low interconnect capacitances and resistances. The first chip comprises an arithmetic logic unit (ALU), at least one register, a stack pointer, a program counter, and an index register. The second chip comprises a command register, a command decoder, and a timing generator, the command decoder in communication with the first semiconductor chip, the command register responsive to a program memory located outside the device.
Inventors
- 👤 Takashi c/o Seiko Epson Corporation Tsukamoto
- 👤 Sachiyuki c/o Seiko Epson Corporation Abe
- 👤 Tetsuo c/o Seiko Epson Corporation Yabushita
- 👤 Yoshimitsu C/O Seiko Epson Corporation Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 02:51
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7835; H; H10; H10W; H10W70/00; H10W70/20; H10W70/22; H10W70/40; H10W70/453; H10W70/60; H10W70/67; H10W70/688; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W90/00; H10W90/701; H10W70/68; H10W70/682; H10W70/685; H10W72/00; H10W72/01; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/50; H10W72/531; H10W72/536; H10W72/551; H10W72/552; H10W72/5522; H10W72/60; H10W90/20; H10W90/291; H10W90/297; H10W90/721; H10W90/722; H10W90/751; H10W90/754; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
55 words
A semiconductor device, comprising: a substrate (4, 4a); a printed circuit (6) on the substrate; a first semiconductor chip (100) having pads (130a-130x) for wire bonding and contacts (132a-132p) for chip-to-chip interconnection; and a second semiconductor chip (200) having contacts (232a-232p) for chip-to-chip interconnection, the first and second semiconductor chips coupled together via respective contacts.
Claim 2
Dependent Claim
23 words
The device of claim 1, wherein: said coupling of the first and second semiconductor chips is accomplished with a heat-hardened silver paste (2).
Claim 3
Dependent Claim
28 words
The device of claim 1, wherein: respective contacts (132a-132p, 232a-232p) on the first and second semiconductor chips (100, 200) are coupled together via an anisotropic conductive material (9).
Claim 4
Dependent Claim
91 words
A semiconductor device, comprising: a substrate (4); a printed circuit (6) on the substrate; a first semiconductor chip (100) having pads (140₁-140₂₈) for bonding; and a second semiconductor chip (200) having pads (240₁-240₁₀) for bonding; and a flexible circuit (8) having a first plurality of printed wires (9') that electrically couple pads on the first semiconductor chip with pads on the second semiconductor chip, the flexible circuit having a second plurality of printed wires (9') that electrically couple pads on the second semiconductor chip with the printed circuit on the substrate.
Claim 5
Independent Claim
23 words
The device of any of the preceding claims, wherein: the first and second semiconductor chips (100, 200) are encapsulated in an epoxy resin.
Claim 6
Independent Claim
25 words
The device of any of the preceding claims, wherein: the first and second semiconductor chips (100, 200) each have active surfaces the face one another.
Claim 7
Dependent Claim
263 words
A semiconductor device packaging system, comprising: a first package (13) having; first, second, and third ceramic layers (16c, 16b, 16a); a plurality of connector pins (18a-18x) in the first ceramic layer (16c); a plurality of sockets (30a-30n) in the third ceramic layer (16a); a first semiconductor chip (100) mounted in a cavity (14a) in the second and third ceramic layers; a first lid (19) that covers the first semiconductor chip; a first connection means for electrically connecting the first semiconductor chip to respective sockets, the connection means comprising bonding wires (15b), plated through-holes (17c) in the third ceramic layer (16a), and printed circuits (14c); a second connection means for electrically connecting the first semiconductor chip to respective connector pins, the connection means comprising bonding wires (15a), plated through-holes (17a, 17b) in the first and second ceramic layers (16c, 16b), and printed circuits (14b); a second package (20) having; fourth, fifth, and sixth ceramic layers (22, 24, 26); a plurality of connector pins (28a-28n) in the fourth ceramic layer (22) such that they mate with the plurality of sockets (30a-30n) in the third ceramic layer (16a) of the first package (13); a second semiconductor chip (200) mounted in a cavity (24a) in the fifth and sixth ceramic layers (24, 26); a second lid (29) that covers the second semiconductor chip; a third connection means for electrically connecting the second semiconductor chip to respective connector pins in the fourth ceramic layer, the connection means comprising bonding wires (25a, 25b), plated through-holes (27a, 27b) in the fourth and fifth ceramic layers, and printed circuits (24b, 24c).
Claim 8
Dependent Claim
218 words
A semiconductor device packaging system, comprising: a first package having; first, second, and third ceramic layers; a plurality of connector pins in the first ceramic layer; a plurality of sockets in the third ceramic layer; a first semiconductor chip mounted in a cavity in the second and third ceramic layers; a first lid that covers the first semiconductor chip; a first connection means for electrically connecting the first semiconductor chip to respective sockets, the connection means comprising bonding wires, plated through-holes in the third ceramic layer, and printed circuits; a second connection means for electrically connecting the first semiconductor chip to respective connector pins, the connection means comprising bonding wires, plated through-holes in the first ceramic layer, and printed circuits; a second package having; fourth, fifth, and sixth ceramic layers; a plurality of connector pins in the fourth ceramic layer such that they mate with the plurality of sockets in the third ceramic layer of the first package; a second semiconductor chip mounted in a cavity in the fifth and sixth ceramic layers; a second lid that covers the second semiconductor chip; a third connection means for electrically connecting the second semiconductor chip to respective connector pins in the fourth ceramic layer, the connection means comprising bonding wires, plated through-holes in the fourth ceramic layer, and printed circuits.
Claim 9
Independent Claim
83 words
The device of any of the preceding claims, wherein: the first semiconductor chip (100) comprises an arithmetic logic unit (102), at least one register (110, 112), a stack pointer (120), a program counter (114), and an index register (116, 118); and the second semiconductor chip (200) comprises a command register (202), a command decoder (204), and a timing generator (206), said command decoder in communication with the first semiconductor chip, said command register responsive to a program memory (302) located outside the device.
Claim 10
Dependent Claim
37 words
The device of claim 9, wherein: said program counter (114) comprises a program counter bank (114a), a program counter page (114b), a program counter step (114c), a new bank pointer (114d), and a new page pointer (114e).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.