EP0495642A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Error detection circuit and method
Assignee: Xilinx Inc
•
Filing: 1992-01-15
•
Granted: —
•
Expires: 2012-01-15
Abstract
Abstract The invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session.
Inventors
- 👤 Charles R. Erickson
- 👤 Philip M. Freidin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:06
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; H03M13/091; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
92 words
A structure for detecting an error in a stream of bits comprising: means for receiving the stream of bits; means for generating a plurality of error check bits from the stream of bits, at least one bit of the error check bits being a function of all previously transmitted bits in the stream of bits; means for testing a subset of the error check bits including the at least one bit; and means for counting bits in the stream bits and at a given count reading the means for testing a subset.
Claim 2
Dependent Claim
25 words
A structure as claimed in claim 1 in which the means for generating error check bits comprises a CRC polynomial generator or a checksum generator.
Claim 3
Dependent Claim
47 words
A structure as claimed in claim 1 or 2 in which the means for testing a subset of the error check bits comprises means for testing a first subset of error check bits, the structure comprising means for testing a second subset of the error check bits.
Claim 4
Dependent Claim
18 words
A structure as claimed in claim 3 in which the second subset is longer than the first subset.
Claim 5
Dependent Claim
16 words
A structure as claimed in claim 4 in which the second subset includes the first subset.
Claim 6
Dependent Claim
21 words
A structure as claimed in claim 4 or 5 in which the second subset comprises all of the error check bits.
Claim 7
Dependent Claim
32 words
A structure as claimed in any preceding claim in which the means for generating error check bits comprises means for loading an initial value into the means for generating error check bits.
Claim 8
Dependent Claim
14 words
A structure as claimed in claim 7 in which the initial value is zero.
Claim 9
Dependent Claim
32 words
A structure as claimed in claim 1 comprising at lest a second means for generating a plurality of error check bits, and means for selecting from a plurality of means for generating.
Claim 10
Dependent Claim
88 words
A structure as claimed in claim 9 in which the means for generating error check bits is a CRC polynomial shift register having a plurality of XOR gates, each of which receives on one input lead the output from one stage of the shift register and provides an output which is input to a next stage of the shift register, and means for selecting between applying a logical zero and a function of bits in the data stream to the other lead of each of the XOR gates.
Claim 11
Dependent Claim
46 words
A structure as claimed in claim 9 in which one of the means for generating error check bits is a CRC polynomial shift register and another of the means for generating check bits is means for reading a selected string of bits from the data stream.
Claim 12
Dependent Claim
49 words
A structure as claimed in claim 9 in which the means for selecting from a plurality of means for generating comprises a control register loaded from the stream of bits and providing a select output controlling a multiplexer into which are input a plurality of alternative error detecting results.
Claim 13
Dependent Claim
31 words
A structure as claimed in any preceding claim in which the means for counting comprises a counter, the counter being loaded from the stream of bits and providing the given count.
Claim 14
Dependent Claim
20 words
A structure as claimed in any one of claims 1-12 in which the means for counting comprises a shift register.
Claim 15
Independent Claim
152 words
A method of detecting an error in a stream of data bits comprising the steps of: at a transmit end, generating from each successive data bit in the stream of data bits an error checkword having the property that subset of the error checkword is a function of all previous bits in the stream of data bits, periodically forming transmission blocks each comprising a frame of data from the stream of data bits and the subset of the error checkword; transmitting each of the transmission blocks to a receive end; at the receive end: receiving the transmission blocks; recalculating the error checkword from the transmission blocks; and comparing a subset of the error checkword generated at the receive end to the subset of the error checkword generated at the transmit end; whereby each time the subsets are compared, it is likely that undetected errors in any previous transmission blocks will be detected.
Claim 16
Dependent Claim
68 words
A method as claimed in claim 15 in which the subset comprises a first subset and comprising the steps of: periodically inserting into the bit stream a second subset of the error checkword, and at points where the second subset is inserted, comparing the second subset of the error checkword generated at the receive end to the second subset of the error checkword generated at the transmit end.
Claim 17
Dependent Claim
30 words
A method as claimed in claim 16 in which the second subset is longer than the first subset and the second subset is checked less frequently than the first subset.
Claim 18
Dependent Claim
22 words
A method as claimed in claim 12 in which the second subset is checked at the end of the stream of bits.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.