Variable page size per entry translation look-aside buffer

Claim 2

The TLB of claim 1 wherein said means for storing an indication of a page size comprises a content addressable memory (CAM) having inputs coupled to a virtual address bus and having match outputs coupled to a memory array of said memory locations.

Claim 3

The TLB of claim 2 wherein said means for providing a variable number of bits comprises a multiplexer having first inputs coupled to said memory array, second inputs coupled to a portion of said virtual address bus and select inputs coupled to said CAM.

Claim 4

The TLB of claim 2 wherein at least a portion of the positions for the entries of said CAM have two bits for storing values to provide a match signal on one of said match outputs for a 0 input, a match for a 1 input, and a match for any input.

Claim 5

The TLB of claim 2 further comprising means for coupling each of said match outputs back to a read input for each of said entries in said CAM.

Claim 6

The TLB of claim 5 wherein said means for coupling comprises a plurality of multiplexers, each multiplexer having an output coupled to a read line for an entry, a first input coupled to a match output for said entry and a second input coupled to a read input for said entry.

Claim 7

The TLB of claim 4 wherein each entry of said TLB has a portion of positions with only one bit stored.

Claim 8

The TLB of claim 4 further comprising: a mask register for storing a value indicating a page size; logic means, having inputs coupled to a data bus and said mask register, and outputs coupled to data I/O lines of said CAM, for writing an always match value to positions in an entry corresponding to the value in said mask register.

Claim 9

A translation look-aside buffer (TLB) comprising: a physical array with a plurality of memory locations for storing physical addresses corresponding to input virtual addresses; a content addressable memory (CAM) having inputs coupled to a virtual address bus and having match outputs coupled to said physical array, wherein at least a portion of the positions for the entries of said CAM have two bits for storing first values to provide a match signal on one of said match outputs for a 0 input, second values for a match for a 1 input, and third values for a match for any input; and means, responsive to said third values in said CAM for providing a variable number of bits of said physical address as an output address, the remaining bits of said output address being bits of said virtual address.

Claim 10

The TLB of claim 9 wherein said means for providing a variable number of bits comprises a multiplexer having first inputs coupled to said physical array, second inputs coupled to a portion of said virtual address bus and select inputs coupled to said CAM.

Claim 11

The TLB of claim 9 wherein said positions in said CAM having two bits each comprise: a first memory cell for storing a first bit value and its inverse; a second memory cell for storing a second bit value and its inverse; a virtual address bit line; an inverse virtual address bit line; first means for providing a signal to one of said match outputs responsive to signals on said first memory cell and said virtual address bit line; and second means for providing a signal to said one of said match outputs responsive to signals on said second memory cell and said inverse virtual address bit line.

Claim 12

The TLB of claim 11 wherein said first means for providing comprises: a first transistor having a first control lead coupled to said virtual address bit line, a second lead coupled to a match output and a third lead; and a second transistor having a first control lead coupled to said first memory cell, a second lead coupled to said third lead of said first transistor, and a third lead coupled to ground.

Claim 13

The TLB of claim 11 further comprising a first sense amplifier coupled to said first memory cell and a second sense amplifier coupled to said second memory cell.

Claim 14

The TLB of claim 9 further comprising: a mask register for storing a value indicating a page size; logic means, having inputs coupled to a data bus and said mask register, and outputs coupled to data I/O lines of said CAM for said entries having two bits, for writing an always match value to positions in an entry corresponding to the value in said mask register.

Claim 15

The TLB of claim 9 further comprising means for coupling each of said match outputs back to a read input for each of said entries in said CAM.

Claim 16

The TLB of claim 15 wherein said means for coupling comprises a plurality of multiplexers, each multiplexer having an output coupled to a read line for an entry, a first input coupled to a match output for said entry and a second input coupled to a read input for said entry.