EP0497577A2
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EP
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High breakdown voltage semiconductor device
Assignee: Toshiba Corp
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Filing: 1992-01-29
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Granted: —
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Expires: 2012-01-29
Abstract
Abstract A high breakdown voltage semiconductor device comprising a semiconductor substrate (1) an insulating layer (2) formed on the semiconductor substrate (1), a high resistance semiconductor layer (4) formed on the insulating layer (2), an isolation region formed in the high resistance semiconductor layer (4), an element region formed in the high resistance semiconductor layer (4) isolated by the isolation region in a lateral direction, a first low resistance region (6) of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region (7) of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region (6) and the second low resistance region (7) is completely depleted when voltage is applied between the first and second low resistance regions (6, 7).
Inventors
- 👤 Tomoko c/o Intellectual Property Div. Matsudai
- 👤 Akio c/o Intellectual Property Div. Nakagawa
- 👤 Norio c/o Intellectual Property Div. Yasuhara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 09:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D30/657; H10D12/00; H10D12/411; H10D12/421; H10D18/00; H10D18/251; H10D18/40; H10D18/60; H10D18/65; H10D18/655; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/601; H10D30/603; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/111; H10D64/112; H10D64/115; H10D64/117; H10D64/118; H10D8/00; H10D8/411; H10D86/00; H10D86/201; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
156 words
A high breakdown voltage semiconductor device comprising: a semiconductor substrate (1); an insulating layer (2) formed on said semiconductor substrate (1); a high resistance semiconductor layer (4) formed on said insulating layer (2); an isolation region formed in said high resistance semiconductor layer (4); an element region formed in said high resistance semiconductor layer (4) isolated by said isolation region in a lateral direction; a first low resistance region (6) of a first conductivity type formed in a central surface portion of said element region; and a second low resistance region (7) of a second conductivity type formed in a peripheral surface portion of said element region, wherein dose of impurities in said element region is set such that a portion of said element region between said first low resistance region (6) and said second low resistance region (7) is completely depleted when voltage is applied between said first and second low resistance regions (6, 7).
Claim 2
Dependent Claim
25 words
The device according to claim 1, characterized in that said dose of impurities in said element region is 0.1 × 10¹² to 3 × 10¹²/cm.
Claim 3
Dependent Claim
34 words
The device according to claim 1, further comprising a third low resistance region (10) of a first conductivity type formed at a boundary surface portion between said insulating layer (2) and said element region.
Claim 4
Dependent Claim
28 words
The device according to claim 1, characterized in that said first low resistance region (6) or said low second resistance region (7) reaches to said insulating layer (2).
Claim 5
Dependent Claim
19 words
The device according to claim 1, characterized in that said isolation region is formed of an insulating member (3).
Claim 6
Dependent Claim
18 words
The device according to claim 1, characterized in that said isolation region is formed of a pn junction.
Claim 7
Dependent Claim
21 words
The device according to claim 1, characterized in that said insulating layer (2) has a thickness of 1 µm or more.
Claim 8
Dependent Claim
21 words
The device according to claim 1, characterized in that said insulating layer (2) has a thickness of 2 µm or more.
Claim 9
Dependent Claim
172 words
A high breakdown voltage semiconductor device comprising: a semiconductor substrate (1); an insulating layer (2) formed on said semiconductor substrate (1); a high resistance semiconductor layer (3) formed on said insulating layer (2); an isolation region formed in said high resistance semiconductor layer; an element region formed in said high resistance semiconductor layer isolated by said isolation region in a lateral direction from said isolation region; a first low resistance region (4) of a first conductivity type formed in a region extending from a surface of said element region to said insulating layer (2); and a second low resistance region (5) of a second conductivity type formed in a region extending from a surface of said element region to said insulating layer (2), wherein dose of impurities in said element region is set such that a portion of said element region between said first low resistance region (4) and said second low resistance region (5) is completely depleted when voltage is applied between said first and second low resistance regions (4, 5).
Claim 10
Dependent Claim
159 words
A lateral type insulated gate bipolar transistor comprising: a semiconductor substrate (301); an insulating layer (302) formed on said semiconductor substrate (301); a high resistance semiconductor layer (303) formed on said insulating layer (302); an isolation region formed in said high resistance semiconductor layer; an element region formed in said high resistance semiconductor layer isolated by said isolation region in a lateral direction; a first low resistance region (312) of a first conductivity type formed in said element region and constituting a drain region; a second low resistance region (311) of a second conductivity type formed in said element region; and a source region (313) of a first conductivity type formed in said second low resistance region (311), wherein dose of impurities in said element region is set such that a portion of said element region between said source region and said drain region is completely depleted when voltage is applied between said source region and said drain region.
Claim 11
Dependent Claim
186 words
A high breakdown voltage semiconductor device comprising: a semiconductor substrate (301); an insulating layer (302) formed on said semiconductor substrate (301); a high resistance semiconductor layer (303) formed on said insulating layer (302); an isolation region formed in said high resistance semiconductor layer (303); an element region formed in said high resistance semiconductor layer (303) isolated by said isolation region in a lateral direction; a first low resistance region (304) of a first conductivity type formed in said element region; and a second low resistance region (305) of a second conductivity type formed in a surface portion of said element region to be separated from said first low resistance region (303), wherein when voltage is applied between said first low resistance region (304) and said second low resistance region (305) and both potential of said first low resistance region (304) and that of said second low resistance region (305) are higher than potential of said semiconductor substrate (301), a channel region of a second conductivity type is formed in the bottom portion of said element region, whereby influence of potential of said semiconductor substrate is shielded.
Claim 12
Dependent Claim
28 words
The device according to claim 11, characterized in that said first low resistance region (304) or said second low resistance region (305) reaches to said insulating layer (302).
Claim 13
Dependent Claim
51 words
The device according to claim 11, characterized in that an impurity region having lower impurity concentration than that of said first low resistance region (304) or said second low resistance region (305) is formed close to or contacting said first low resistance region (304) or said second low resistance region (305).
Claim 14
Dependent Claim
36 words
The device according to claim 11, characterized in that a gate insulating layer is formed on a surface of said element region between said first low resistance region (304) and said second low resistance region (305).
Claim 15
Dependent Claim
22 words
The device according to claim 14, characterized in that said gate insulating layer (314) has a thickness of 0.3 µm or less.
Claim 16
Dependent Claim
20 words
The device according to claim 14, characterized in that a high resistance layer is formed on said gate insulating layer.
Claim 17
Dependent Claim
34 words
The device according to claim 11, characterized in that the high resistance layer is formed on a surface of said element region between said first low resistance region and said second low resistance region.
Claim 18
Dependent Claim
21 words
The device according to claim 11, characterized in that dose of impurities is 1.0 × 10¹⁰ to 2.0 × 10¹² /cm².
Claim 19
Dependent Claim
52 words
The device according to claim 1, characterized in that a distance between the second low resistance region and the insulating layer is a value represented by the 20 ε/qC N (cm) or less. ε: 1.05 × 10⁻¹² (F/cm) q: 1.6 × 10⁻¹⁹ (C) CN: impurity concentration of the high resistance semiconductor layer.
References Cited (Backward Citations)
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