EP0504537A1
Expired / Lapsed
EP
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Method and apparatus for the testing and evaluation of geographically distributed telecommunication networks
Assignee: International Business Machines Corp
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Filing: 1991-03-22
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Granted: —
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Expires: 2011-03-22
Abstract
Abstract The dynamic functional behavior of geographically distributed fast packet switching systems, including those which accommodate high-priority circuit switched traffic and low-priority packet switched traffic, can be tested in real-time by sending test packets from one or more source nodes through the system to specific destinations that comprise a test packet analyzer. The test packets have the same structure as the data packets but in their payload portion carry the entire information required to perform the testing. The nature of that test information depends on the characteristics of a set of predefined system errors the verification system is supposed to identify. For example, for detecting a specific set of errors encompassing packet loss, packet duplication, wrong packet sequence, packet at wrong output, packet corruption, packet length error, and unacceptable packet delay, the test information would include an input address indicating the source of the test packet, a sequence number defining the order in which the packet should arrive at the destination, time bits relating to the packet length and/or to the expected packet transmission delay, and a cyclic redundancy code which covers the entire contents of the test packet, including its control portion. Each analyzer at a receiving station operates autonomously from the senders and processes all received traffic in real-time: this enables it to recognize all defined system errors, even those occurring with very low probability, at the packet level.
Inventors
- 👤 Antonius Dr. Engbersen
- 👤 Marco Heddes
- 👤 Andreas Dr. Herkersdorf
- 👤 Ronald Luijten
- 👤 Ernst Dr. Rothauser
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 13:23
CPC Classifications
H; H04; H04L; H04L43/00; H04L43/50; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5628
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
181 words
Method for testing and evaluating the dynamic functional behavior of geographically distributed telecommunication networks, in particular fast packet switching networks comprising a plurality of transmitting stations, receiving stations and communication links connecting those stations for the transmission of traffic organized in the form of packets, wherein the packets contain a control block and a payload portion, the latter being devoted to carrying the user information, characterized by the following steps: - defining the primitive functional building blocks, such as paths, between the inputs and outputs of the network, - defining a set of target errors which the testing and evaluation is supposed to detect, - passing, during a testing and evaluation phase and/or during normal operation of the network, test packets around the network which contain, in addition to the information normally contained in their control block, in their payload portion all information relevant to their testing and evaluation task, instead of the user information normally contained in said payload portion, and - analyzing the test packets arriving at the output port of their path of transmission for any unexpected results.
Claim 2
Dependent Claim
50 words
Method in accordance with claim 1, characterized in that the information relevant to the testing and evaluation task of the test packets and contained in the payload portion of the test packets comprises at least an input address, a sequence number, time bits, and a cyclic redundancy check (CRC) code.
Claim 3
Dependent Claim
49 words
Method in accordance with claim 1, characterized in that the information contained in the control block of the packets at least encompasses an output address and a type bit, said output address defining the destination of the packet, said type bit indicating the priority level associated with the packet.
Claim 4
Dependent Claim
81 words
Method in accordance with claim 2, characterized in that said input address defines the source of the test packet, that the sequence number indicates the order in which the test packets are sent out from a particular source, that the time bits define the transmission delay of the test packet through the network, and that the CRC code ensures the correctness of the entirety of the information contained in the control block and in the payload portion of the test packet.
Claim 5
Dependent Claim
50 words
Method in accordance with claim 1, characterized in that said set of target errors is defined to comprise at least two of the following: packet loss, packet duplication, packet arrival in wrong sequence, packet arrival at wrong output, packet arrival with wrong packet length, corrupted packet contents, wrong packet delay.
Claim 6
Dependent Claim
120 words
Method in accordance with claim 5, characterized in that the contents of the control block and payload portion of the test packet are considered, alone or in combination, to test the network for one or more of these errors: - sequence number and input address for the determination of packet loss, packet duplication, and packet arrival in wrong sequence; - output address for the determination of arrival of a test packet at a wrong output; - type bit for the determination of a packet arriving with a wrong packet length; - time bits for the determination of a packet arriving with a wrong packet delay; and - CRC code for the determination of a packet arriving with corrupted packet contents.
Claim 7
Dependent Claim
39 words
Method in accordance with claim 1, characterized in that sequences of test packets are simultaneously sent from several input ports to several output ports, whereby the traffic load conditions are varied between any two successive transmissions of test packets.
Claim 8
Dependent Claim
73 words
Method in accordance with claim 1, characterized in that the test packets prior to their transmission are stored in separate memory locations at the transmitter, and that for their transmission at a reduced transmission rate, the transputer of the transmitter sends the memory address of the first byte of the test packet to the transmitter hardware, and that the actual transmission of the test packet is performed by the transmitter hardware control logic.
Claim 9
Dependent Claim
49 words
Method in accordance with claim 1, characterized in that the test packets have a fixed length determined by the type of traffic with which they are associated; for high-priority voice traffic the test packet length is 8 bytes, whereas for low-priority data traffic the packet length is 32 bytes.
Claim 10
Dependent Claim
49 words
Method in accordance with claim 1, characterized in that the test packets have a fixed length determined by the type of traffic with which they are associated; for high-priority voice traffic the test packet length is 8 bytes, whereas for low-priority data traffic the packet length is 53 bytes.
Claim 11
Dependent Claim
113 words
Verification apparatus for testing and evaluating the dynamic functional behavior of geographically distributed telecommunication networks, in particular fast packet switching networks comprising pluralities of transmitting stations, receiving stations and communication links connecting those stations for the transmission of traffic organized in the form of packets, characterized in that it comprises a system environment portion, a result analyzer portion, a global controller and a test case generation portion, said system environment portion including a plurality of transmitters associated each with an input port of the packet switching network to be tested, said result analyzer portion including a plurality of receivers each respectively associated with one of the output ports of said packet switching network.
Claim 12
Dependent Claim
104 words
Verification apparatus in accordance with claim 12, characterized in that said transmitters and said receivers are designed as transputers such that one transputer is individually associated with each input port and with each output port of the network to be tested, that a first control transputer is connected to the inputs of all transputers on the transmitter side, that a second control transputer is connected to the inputs of all transputers on the receiver side, and that said global controller comprises a personal computer for user interaction, and a third control transputer for the overall control of the apparatus and/or the test case generation.
Claim 13
Dependent Claim
110 words
Verification apparatus in accordance with claim 12, characterized in that said transputers of said transmitters comprise a first random-access memory (30) associated with the low-priority traffic, and a second random-access memory (31) associated with the high-priority traffic, that each of said memories (30, 31) is respectively connected with a first-in-first-out buffer (35, 34), that a first transmitter controller (32) is connected to said buffers (35,34) for providing a transputer clock signal, and that a second transmitter controller (33) is connected to said buffers (35, 34) and to said memories (30, 31) for providing a switch clock signal and a serial output signal to the packet switching network to be tested.
Claim 14
Dependent Claim
120 words
Verification apparatus in accordance with claim 12, characterized in that said transputers of said receivers comprise a first switch clock-controlled receiver controller (42) having a serial input connected to the associated output port of the packet switching network to be tested and having parallel outputs respectively connected to a plurality of error checkers (36...39) each dedicated to at least one of a set of predetermined target errors, to a packet buffer (40) and to a performance evaluation unit (41), and that the outputs of said error checkers (36...39), said packet buffer (40), and said performance evaluation unit (41) are connected to the inputs of a second transputer clock-controlled receiver controller (43) connected in turn to an external memory interface (23).
References Cited (Backward Citations)
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