← Back to Patent Explorer
EP0505158A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Integrated semiconductor circuit

Assignee: Fujitsu VLSI Ltd
•
Filing: 1992-03-18
•
Granted: —
•
Expires: 2012-03-18
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An integrated semiconductor circuit has a boost circuit (5) that may improve boost operation speed. The boost circuit (5) employs a P-channel type transistor (2) as a driver. The back gate of the P-channel type transistor (2) is connected to a charge-up circuit (8) so that the back gate may be charged to a predetermined level before a boost signal (a) is applied to the driver.

Inventors

  • 👤 Miki c/o FUJITSU VLSI LIMITED Nishimori
  • 👤 Teruo C/O Fujitsu Vlsi Limited Seki

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-06 23:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C5/00; G11C5/14; G11C5/145; G11C8/00; G11C8/08; G11C8/10

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 72 words
An integrated semiconductor circuit employing a boost circuit for generating a voltage higher than a high potential power source, said boost circuit comprising: a P-channel type transistor as a driver for driving a boosted signal(b) with a boost signal (a); and a charge-up means for charging the back gate of said P-channel type transistor to a predetermined level in advance of the application of said boost signal to said P-channel type transistor.
Claim 2
Dependent Claim 112 words
An integrated semiconductor circuit as set forth in claim 1, wherein said boost circuit comprises a N-channel type transistor having the source and a drain connected to said high potential power source; the drain of said N-channel type transistor being connected to the source of said P-channel type transistor; said P-channel type transistor has the drain connected to a substrate, a back gate to which a signal to turn ON said P-channel type transistor before boosting is applied, and a gate to which an input signal is applied and the node between said N-channel type transistor and said P-channel type transistor is connected to the output of a boost signal generating means.
Claim 3
Dependent Claim 23 words
An integrated semiconductor circuit as set froth in claim 2, wherein said boost signal generating means comprises an oscillation means and a capacitor.
Claim 4
Dependent Claim 30 words
An integrated semiconductor circuit as set forth in claim 1, wherein said charge-up means for the back gate of said P-channel type transistor comprises an oscillation means and a capacitor.
Claim 5
Dependent Claim 28 words
An integrated semiconductor circuit as set forth in claim 1, wherein said charge-up means for the back gate of said P-channel type transistor comprises a constant voltage source.
Claim 6
Dependent Claim 45 words
An integrated semiconductor circuit as set forth in claim 4, wherein said charge-up means further comprises an N-channel type transistor having the source and gate connected to the high potential power source and the drain connected to the back gate of said P-channel type transistor.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag