EP0508577A1
Expired / Lapsed
EP
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Address translation mechanism
Assignee: International Business Machines Corp
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Filing: 1992-02-26
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Granted: —
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Expires: 2012-02-26
Abstract
Abstract A dynamic address translation mechanism uses a single translation look aside buffer (TLB) 30 for pages of various sizes. The single TLB is supported by a small amount of special hardware. This hardware includes logic for detecting a page size prior to translation and generating a mask 36. The logic selects a set of virtual address bits for addressing the entries in the TLB. Parts of the virtual address are masked and merged with the address read out of the TLB to form the real address 37.
Inventors
- 👤 Jamshed Hormazdyar Mirza
- 👤 Steven Wayne White
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 09:49
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F2212/00; G06F2212/65; G06F2212/652
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
161 words
An address translation mechanism for a virtual storage system in a data processing system which supports multiple size pages, comprising means for storing a virtual address to be translated to a real address in storage, a single translation-look aside buffer (30) storing translation entries for the multiple size pages, a number of bits in an entry being independent of page size and a number of page sizes supported by the address translation mechanism being such that the ratio of maximum size to minimum size is less than or equal to a number of translation look-aside buffer congruence classes, logic means for selecting a first subset of virtual address bits for addressing the translation entries in the translation look aside buffer and for selecting a second subset of the virtual address bits, and means for merging the second subset of virtual address bits with an address read out of the translation look aside buffer to form a portion of a real address.
Claim 2
Dependent Claim
41 words
Mechanism according to claim 1, wherein the logic means includes mask generation means for using a specified one of said multiple page sizes prior to translation to generate a mask (36), logic means masking a subset of the virtual address bits.
Claim 3
Dependent Claim
27 words
Mechanism according to claim 2, wherein the logic means further includes shifter means (31) for shifting a portion of the virtual address to generate the first subset.
Claim 4
Dependent Claim
45 words
Mechanism according to claim 1, 2 or 3, wherein each translation look-aside buffer entry consists of a 12-bit tag value and a 20-bit real address field and the multiple size pages range from 4kB to 1MB in size specified by a 4-bit page size code.
Claim 5
Dependent Claim
60 words
Mechanism according to claim 4, as appendant to claim 3, wherein the 4-bit page size code is used by the mask generation means to generate the mask and controls the shifter means for shifting the portion of the virtual address to generate the first subset of virtual address bits for addressing the translation entries in the translation look aside buffer.
Claim 6
Dependent Claim
91 words
Mechanism according to claim 1, wherein the data processing system supports two pages sizes and the logic means comprises first multiplexer means (38) for selecting either the first subset or the second subset of virtual address bits for addressing the translation entries in the translation look-aside buffer, and second multiplexer means (39) for selecting either a first portion of an address read out of the translation look-aside buffer or the second subset of virtual address bits for merging a second portion of the address read out of the translation look-aside buffer.
Claim 7
Dependent Claim
23 words
Mechanism according to claim 6, wherein each translation look-aside buffer entry consists of a 12-bit tag value and a 20-bit real address field.
References Cited (Backward Citations)
US3675215A
Cited
US4766537A
Cited
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