EP0540206A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Information handling apparatus allowing direct memory access
Assignee: International Business Machines Corp
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Filing: 1992-10-12
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Granted: —
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Expires: 2012-10-12
Abstract
Abstract A direct memory access controller for allowing direct access to memory, the direct memory access controller being connected to receive control information from a processor portion, to provide data information to a system memory and an I/O bus and to receive data information from the system memory and the I/O bus. The direct memory access controller includes a register circuit which receives the data information, holds the data information and provides the data information, a backup circuit, the backup circuit which receives and stores data information from the register circuit, and a direct memory access control circuit which receives the control information from the processor circuit and provides control information to the register circuit and the backup circuit. The backup circuit stores data information from the register circuit while the register circuit receives, holds and provides alternate data information based upon control information which is received from the direct memory access control circuit.
Inventors
- 👤 Nader Amini
- 👤 Bechara Foud Boury
- 👤 Terence Joseph Lohman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 02:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
174 words
An information handling apparatus for allowing direct access of memory comprising a processor portion, a system memory, an input/output bus, and a direct memory access controller connected to receive control information from the processor portion, to provide data information to the system memory and the I/O bus and to receive data information from the system memory and the I/O bus, said direct memory access controller including a register circuit connected to receive said data information, to hold said data information and to provide said data information, a backup circuit, said backup circuit being connected to receive and store data information from said register circuit, and a direct memory access control circuit, said direct memory access control circuit being connected to receive said control information from said processor circuit and to provide control information to said register circuit and said backup circuit, said backup circuit storing data information from said register circuit while said register circuit receives, holds and provides alternate data information based upon control information received from said direct memory access control circuit.
Claim 2
Dependent Claim
45 words
The apparatus of claim 1 wherein said direct memory access control circuit includes a direct memory access cycle execution circuit, said direct memory access cycle execution circuit providing high level control of said register circuit and said backup circuit by generating high level control information.
Claim 3
Dependent Claim
31 words
The apparatus of claim 2 wherein said direct memory access cycle execution circuit includes a direct memory access control state machine, said control state machine providing said high level control information.
Claim 4
Dependent Claim
44 words
The apparatus of claim 3 wherein said direct memory access control state machine includes a supervisory state machine and an execution state machine, said supervisory state machine controlling initialization and completion of transfers, and said execution state machine controlling a direct memory access transfer.
Claim 5
Dependent Claim
68 words
The apparatus of claim 4 wherein said supervisory state machine determines if a direct memory access transfer is an initial transfer, if the transfer is an initial transfer then control is provided to said execution state machine, the transfer is executed, and control is returned to said supervisory state machine, said supervisory state machine controlling storing any residual data information from said register circuit into said backup circuit.
Claim 6
Dependent Claim
80 words
The apparatus of claim 4 wherein said supervisory state machine determines if a direct memory access transfer is a subsequent transfer, if the transfer is a subsequent transfer then data information is provided from said backup circuit to said register circuit, control is provided to said execution state machine, the transfer is executed, and control is returned to said supervisory state machine, said supervisory state machine controlling storing any residual data information from said register circuit into said backup circuit.
Claim 7
Dependent Claim
73 words
The apparatus of claim 4 wherein said direct memory access control circuit further includes a backup control circuit, said backup control circuit working in conjunction with said control state machine to backup and retrieve data information between said register circuit and said backup circuit, said backup controller circuit generating backup control signals under control of said control state machine, said backup control signals being provided to said register circuit and said backup circuit.
Claim 8
Dependent Claim
70 words
The apparatus of claim 2 wherein said direct memory access control circuit further includes a control signal generator circuit, said control signal generator circuit generating direct memory access control signals based upon said high level control information, said direct memory access control signals being provided to said register circuit, said direct memory access control signals being stored in said backup circuit along with said data information from said register circuit.
Claim 9
Dependent Claim
27 words
The apparatus of claim 8 wherein said direct memory access control signals include a mode control signal, said mode control signal indicating a mode of DMA transfer.
Claim 10
Dependent Claim
51 words
The apparatus of claim 8 wherein said direct memory access control signals includes register read and write pointer signals, said register read pointer signal indicating from where to read data information in said register circuit, said register write pointer signal indicating to where to write data information in said register circuit.
Claim 11
Dependent Claim
36 words
The apparatus of claim 8 wherein said direct memory access control signals include first and second address information, said first and second address information indicating a source and a destination of a direct memory access transfer.
Claim 12
Dependent Claim
55 words
The apparatus of claim 1 wherein said controller includes a plurality of direct memory access channels, each channel being capable of independently directly accessing memory, and said backup circuit includes a plurality of backup channels corresponding to said plurality of direct memory access channels, each backup channel storing said data information from said register circuit.
Claim 13
Dependent Claim
20 words
The apparatus of claim 1 wherein data information is transferred between said register circuit and said backup circuit in parallel.
Claim 14
Dependent Claim
17 words
The apparatus of claim 1 wherein said backup circuit stores control information relating to said data information.
Claim 15
Dependent Claim
46 words
The apparatus of claim 1 wherein said register circuit is a first in, first out register circuit, said data information which is held in said register circuit being retrieved from said register circuit in the order that said data information is provided to said register circuit.
Claim 16
Dependent Claim
40 words
The apparatus of claim 15 wherein said first in, first out register circuit is 20-bytes wide, and said backup circuit is 20-bytes wide allowing said data information held in said register circuit to be directly provided to said backup circuit.
Claim 17
Dependent Claim
22 words
The apparatus of claim 16 wherein said backup circuit includes locations to store control information relating to said 20-byte wide data information.
Claim 18
Dependent Claim
40 words
The appartus of claim 15 wherein said first in, first out register circuit is 32-bytes wide, and said backup circuit is 32-bytes wide allowing said data information held in said register circuit to be directly provided to said backup circuit.
Claim 19
Dependent Claim
22 words
The apparatus of claim 16 wherein said backup circuit includes locations to store control information relating to said 32-byte wide data information.
References Cited (Backward Citations)
No citation records indexed.
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