Non-volatile semiconductor memory device

Claim 2

The semiconductor memory device according to claim 1, characterized in that said predetermined voltage (V MC ) is substantially equal to a minimum value (V TN (E) min ) of threshold values of those of said memory cells which are electrically erased; and said read means applies the predetermined voltage to all of said row address lines to detect whether or not there is an electrically erased memory cell whose threshold value is lower than the predetermined voltage, thereby to detect if there is an electrically over-erased memory cell.

Claim 3

The semiconductor memory device according to claim 1, characterized in that said read means includes: selecting means (YDEC, Y₁-Y l ) for sequentially selecting said digit lines (D₁-D l ); and means for applying the predetermined voltage (V MC ) to control gates of said memory cells (M₁₁-M 1m ) commonly connected to the digit line (D₁ etc.) which is selected by said selecting means to read out stored data from said memory cell, and detecting whether or not there is an electrically erased memory cell whose threshold value is lower than said predetermined voltage in order to detect if there is an electrically over-erased memory cell.

Claim 4

The semiconductor memory device according to claim 1, characterized in that said read means includes: selecting means (YDEC, Y₁-Y l ) for selecting a digit line (D₁-D l ); and means for applying said predetermined voltage (V MC ) to control gates of said memory cells (M₁₁-M 1m ) commonly connected to said selected digit line (D₁ etc.) to detect if a voltage on said selected digit line drops.

Claim 5

The semiconductor memory device according to claim 1, characterized in that said read means includes: generating means (MCG) for outputting the predetermined voltage; and means (XDEC, MCC), connected to said row address lines (W₁-W N ), for, upon reception an address and said predetermined voltage (V MC ), applying a read voltage (V CC ) to a selected row address line (W₁ etc.) in read mode, applying a write voltage (V PP ) to a selected row address line (W₁ etc.) in write mode, and applying said predetermined voltage (V MC ), supplied from said generating means (MCG), to all of said plurality of row address lines (W₁-W n ) to detect if there is any electrically over-erased memory cell.

Claim 6

The semiconductor memory device according to claim 1, characterized by further comprising erasing means (XDEC, YDEC, Y₁-Y l , ERC) for electrically erasing said plurality of memory cells, after electric erasure of said plurality of memory cells (M₁₁-M lm ) by said erasing means is complete, said read means detects whether or not there is an electrically erased memory cell whose threshold value is lower than said predetermined voltage (V MC ) in order to detect if there is an electrically over-erased memory cell.

Claim 7

The semiconductor memory device according to claim 6, characterized in that said erasing means includes means (S1-S9) for repeating electric erasure of all of said plurality of memory cells until all the threshold values of said plurality of memory cells become equal to or smaller than a given value.

Claim 8

A non-volatile semiconductor memory device characterized by comprising: a plurality of memory cells (M₁₁-M lm ) each for storing data by a change in a threshold value; write means (XDEC, YDEC, Y₁-Y l , WC), connected to said plurality of memory cells, for writing predetermined data in a selected memory cell by setting the threshold value of said selected memory cell higher than the predetermined value; erasing means (XDEC, YDEC, Y,-Y l , ERC), connected to said plurality of memory cells, for electrically erasing said plurality of memory cells; and checking means (MCC, XDEC, YDEC, Y₁-Y l , SA), connected to said plurality of memory cells, for checking if the threshold values of those memory cells electrically erased by said erasing means are equal to or greater than a predetermined reference value.

Claim 9

The semiconductor memory device according to claim 8, characterized in that the reference value (V MC ) is substantially equal to a minimum value (V TN (E) min ) allowable on the design base for the threshold values of those of said memory cells which are electrically erased; and said checking means detects whether or not there is an electrically erased memory cell whose threshold value is lower than the reference value in order to detect if there is an electrically over-erased memory cell.

Claim 10

The semiconductor memory device according to claim 8, characterized in that said checking means applies a voltage equal to the predetermined reference value (V MC ) to gates of said plurality of memory cells to check if there is a memory cell which is turned on in order to detect if there is an electrically over-erased memory cell.

Claim 11

The semiconductor memory device according to claim 8, characterized in that said erasing means includes means (S1-S9) for repeating electric erasure of all of said plurality of memory cells until all the threshold values of said plurality of memory cells become equal to or smaller than a given value.

Claim 12

A memory cell checking method characterized by comprising: an erasing step (S2-S9) of electrically erasing a plurality of memory cells of a memory chip; a checking step (S10-S15) of checking if threshold values of said memory cells are equal to or above a reference value (V MC ), said checking step being performed after completion of said erasing step; and a step (S12) of discriminating said memory chip as a defect when a memory cell whose threshold value is below said reference value (V MC ) is detected in said checking step.

Claim 13

The method according to claim 12, characterized in that said reference value (V MC ) is substantially equal to a minimum value (V TN (E) min ) allowable on the design base for said threshold values of those of said memory cells (M₁₁-M lm ) which are electrically erased.

Claim 14

A memory cell checking method characterized by comprising: a writing step (S1) for writing data in a plurality of memory cells (M₁₁-M lm ) to be electrically erased, thereby setting threshold value of each of said memory cells equal to or greater than a predetermined value, said plurality of memory cells being included in a memory chip and storing data by changing the threshold values; an erasing step (S2) of electrically erasing said plurality of memory cells to be erased to which data are electrically written by said writing step; an erase verify step (S2-S9) for checking the threshold values of said electrically erased memory cells and repeat said erasing step until the threshold value of all of said plurality of memory cells to be erased become equal to or below a first value (V EV ); a checking step (S10-S15) to be performed after detecting that said threshold value of all of said plurality of memory cells to be erased have become equal to or below said first value (V EV ), to check if the threshold values of said plurality of memory cells are equal to or above a second value (V TN (E) min ) smaller than the first value; and a step (S12) of discriminating said memory chip as a defect when a memory cell whose threshold value is below said second value (V TN (E) min ) is detected in said checking step.