EP0548995A2
Expired / Lapsed
EP
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Usage parameter control circuit
Assignee: Fujitsu Ltd
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Filing: 1992-12-28
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Granted: —
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Expires: 2012-12-28
Abstract
Abstract A usage parameter control circuit for effecting a policing control in an ATM transmission network, comprising a time interval measuring unit (10) for measuring a time interval between a currently arrival time of a cell to be judged, and an arrival time of a cell which arrived a reference threshold number (X) of cells before the currently arriving cell arrives; and a judging unit (20) for judging whether or not the measured time interval is shorter than a reference threshold time interval (T), whereby a longer accessing time is allowed and the circuit construction has a flexible expandability. <IMAGE>
Inventors
- 👤 Hiroshi c/o Fujitsu Limited Takeo
- 👤 Michio c/o FUJITSU LIMITED Kusayanagi
- 👤 Kazuo c/o Fujitsu Limited Iguchi
- 👤 Naoaki Yamanaka
- 👤 Yoichi Sato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 17:49
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L12/5602; H04L2012/5629; H04L2012/5631; H04L2012/5636
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
169 words
A usage parameter control circuit for effecting a policing control in an ATM transmission network to restrict transmission of an arriving cell when the arriving cell is in violation of at least one of usage parameters declared by a subscriber, comprising: time interval measuring means (10) for measuring a time interval between a currently arrival time of a cell to be judged as to whether or not the cell is in violation, and an arrival time of a cell which arrived a reference threshold number (X) of cells before the currently arriving cell arrives; and judging means (20) for judging whether or not the measured time interval is shorter than a reference threshold time interval (T), said reference threshold number of cells and said reference threshold time interval (T) being at least a part of said usage parameters declared by the subscriber, the currently arriving cell being judged to be in violation of the usage parameters when the measured time interval is shorter than the predetermined time interval (T).
Claim 2
Dependent Claim
143 words
A usage parameter control circuit as claimed in claim 1, wherein said time interval measuring means comprises a memory (10) for storing the arrival time of the cell which arrived the reference threshold number (X) of cells before the currently arriving cell arrives; and the usage parameter control circuit further comprises cell discarding means (30); said judging means (20) judging, based on the judgement of whether or not the measured time interval is shorter than the reference threshold time interval (T), whether or not the number of cells passed within the reference threshold time interval (T) is larger than the reference threshold number of cells; and said cell discarding means (30) discarding the currently arriving cell when said judging means judges that the number of cells passed within the reference threshold time interval (T) is larger than the reference threshold number of cells.
Claim 3
Dependent Claim
36 words
A usage parameter control circuit as claimed in claim 2, wherein said memory (10) is a logical shift register constructed by a random access memory and pointers for indicating the addresses of said random access memory.
Claim 4
Dependent Claim
38 words
A usage parameter control circuit as claimed in claim 3, further comprising write inhibit means for inhibiting the writing of the currently arrival time into said memory (10) when said cell discarding means discards the currently arriving cell.
Claim 5
Dependent Claim
207 words
A usage parameter control circuit as claimed in claim 1, further comprising : adjacent cell time interval measuring means (11, 12) for measuring an arrival time interval between adjacent cells each time a cell to be judged arrives; a memory (10) for storing the arrival time interval between adjacent cells each time a cell to be judged arrives; and cell discarding means (30); the measured time interval between a currently arrival time of a cell to be judged and an arrival time of a cell which arrived a reference threshold number (X) of cells before the currently arriving cell arrives being obtained by adding the reference threshold number (X) of the arrival time intervals stored in the memory (10); said judging means (20) judging, based on the judgement of whether or not the measured time interval is shorter than the reference threshold time interval (T), whether or not the number of cells passed within the reference threshold time interval (T) is larger than the reference threshold number of cells; and said cell discarding means (30) discarding the currently arriving cell when said judging means judges that the number of cells passed within the reference threshold time interval (T) is larger than the reference threshold number of cells.
Claim 6
Dependent Claim
36 words
A usage parameter control circuit as claimed in claim 5, wherein said memory (10) is a logical shift register constructed by a random access memory and pointers for indicating the addresses of said random access memory.
Claim 7
Dependent Claim
38 words
A usage parameter control circuit as claimed in claim 6, further comprising write inhibit means for inhibiting the writing of the arrival time interval into said memory (10) when said cell discarding means discards the currently arriving cell.
Claim 8
Dependent Claim
80 words
A usage parameter control circuit as claimed in claim 5, wherein the adjacent cell time interval measuring means comprises a timer counter (6) provided to correspond to each cell type information, for counting a time, the count value in the timer counter being input to the memory each time when a cell arrives at the input of the memory, and the count value of the timer counter being reset each time the count value is input to the memory (10).
Claim 9
Dependent Claim
28 words
A usage parameter control circuit as claimed in any one of claims 2 to 8, wherein said memory (10) is provided to correspond to each cell type information.
Claim 10
Dependent Claim
33 words
A usage parameter control circuit as claimed in claim 9, wherein at least one of said reference threshold time interval (T) and said reference threshold number (X) depends on the cell type information.
Claim 11
Dependent Claim
217 words
A usage parameter control circuit for effecting a policing control in an ATM transmission network to restrict the transmission of an arriving cell when the arriving cell is in violation of at least one of usage parameters declared by subscribers, comprising: a plurality of judging units (42₀, ..., 42 m ) provided to respectively correspond to cell types, each for judging whether or not an arriving cell of a corresponding cell type is in violation of corresponding usage parameters declared by a subscriber; each of the judging units comprising: time interval measuring means (10) for measuring a time interval between a currently arrival time of a cell to be judged as to whether or not the cell is in violation, and an arrival time of a cell which arrived a reference threshold number (X) of cells before the currently arriving cell arrives; and judging means (20) for judging whether or not the measured time interval is shorter than a reference threshold time interval (T), said reference threshold number of cells and said reference threshold time interval (T) being at least a part of said usage parameters declared by the subscriber, the currently arriving cell being judged to be in violation of the usage parameters when the measured time interval is shorter than the predetermined time interval (T).
Claim 12
Dependent Claim
124 words
A usage parameter control circuit as claimed in claim 1, wherein said time interval measuring means (10) comprises; a bridge memory (BM) for storing, in a time sequence, at least one cell type of cells arriving at the input of the bridge memory; and first pointer holding means (XP) for holding a first pointer indicating a storing position of a cell type, stored in the bridge memory, of a cell, the stored cell type being the same as the cell type of an arriving cell to be judged; and said judging means comprises a control unit (CTL) for judging whether or not an arriving cell to be judged is in violation by controlling the bridge memory (BM) and the first pointer holding means (XP).
Claim 13
Dependent Claim
93 words
A usage parameter control circuit as claimed in claim 12, wherein said control unit (CTL) comprises comparing means for comparing the time interval determined, each time a cell to be judged arrives at the input of the bridge memory (BM), by a difference between the storing position indicated by said first pointer holding means and the input position of the bridge memory with the reference threshold time interval (T), whereby the arriving cell is judged to be in violation when the measured time interval is shorter than the reference threshold time interval (T).
Claim 14
Dependent Claim
57 words
A usage parameter control circuit as claimed in claim 13, wherein when the control unit (CTL) judges that the arriving cell is not in violation, the control unit (CTL) controls the first pointer holding means (XP) to store the position information of the cell type of the arriving cell at the input of the bridge memory (BM).
Claim 15
Dependent Claim
97 words
A usage parameter control circuit as claimed in claim 13, further comprising counting means (CM) for counting the number of cell types or cells, the cell types being stored in the bridge memory (BM), the cell types of the cells being the same as the cell type of an arriving cell to be judged; the control unit (CTL) controlling the counting means (CM) to count the number of cell types of the cells up to a certain number n from a cell type at the input of the bridge memory (BM) to an already stored cell type.
Claim 16
Dependent Claim
27 words
A usage parameter control circuit as claimed in claim 15, wherein the certain number n is a reference threshold number (X) of cells declared by a subscriber.
Claim 17
Dependent Claim
48 words
A usage parameter control circuit as claimed in claim 15, wherein when the count value of the counting means (CM) is smaller than the certain number n each time a cell to be judged arrives, the control unit (CTL) judges that the arriving cell is not in violation.
Claim 18
Dependent Claim
68 words
A usage parameter control circuit as claimed in claim 15, wherein the control unit (CTL) controls the first pointer holding means (XP) to store the storing position of the cell type of a cell that arrived the number indicated by the counting means (CM) before arriving the currently arriving cell, the cell type being the same as the cell type of a currently arriving cell to be judged.
Claim 19
Dependent Claim
118 words
A usage parameter control circuit as claimed in claim 18, wherein the bridge memory (BM) comprises: cell type storing areas (VP) for storing cell types; and next pointer storing areas (NP) respectively related to the cell type storing areas (VP), each of the next pointer storing areas (NP) storing a position of a cell type of a cell which arrived next to the arrival of the cell type stored in the related cell type storing area (VP), the control unit (CTL) chains together a plurality of the cell type storing areas of cells, having the same cell type as the cell type of a currently arriving cell to be judged, by using the next pointer storing areas (NP).
Claim 20
Dependent Claim
111 words
A usage parameter control circuit as claimed in claim 19, further comprising: last pointer holding means (LP) for holding the storing position of a cell type of a cell which is most-recently stored in the bridge memory (BM), the cell type being the same as the cell type of the currently arriving cell to be judged; the control unit (CTL) controlling, when an arriving cell is judged not to be in violation, the last pointer holding means (LP) so as to store the position information of the input of the bridge memory (BM) into the next pointer storing area corresponding to the position stored in the last pointer holding means (LP).
Claim 21
Dependent Claim
72 words
A usage parameter control circuit as claimed in claim 20, wherein when the count value of the counting means (CM) is n when a cell to be judged arrives, the control unit (CTL) controls the first pointer holding means (XP) to record the information stored in the next pointer storing area (NP) indicated by the first pointer holding means (XP) in the bridge memory (BM) into the first pointer holding means (XP).
Claim 22
Dependent Claim
55 words
A usage parameter control circuit as claimed in claim 21, wherein the bridge memory comprises at least one flag storing area (F) corresponding to the cell type storing area (VP), the control unit (CTL) controlling the storing area in the bridge memory (BM) to be valid or invalid by using the flag storing area (F).
Claim 23
Dependent Claim
49 words
A usage parameter control circuit as claimed in claim 22, wherein the control circuit (CTL) forcedly changes the contents of the flag storing area (F) in a storing position, which is to be shifted, at the next timing, to the input of the bridge memory (BM), to be invalid.
Claim 24
Dependent Claim
51 words
A usage parameter control circuit as claimed in claim 22, wherein the control circuit (CTL) forcedly changes the contents of the flag storing area (F) of a cell to be judged, which arrived before arriving the cell at the position indicated by the first pointer holding means (XP), to be invalid.
Claim 25
Dependent Claim
31 words
A usage parameter control circuit as claimed in claim 22, wherein the control circuit (CTL) uses a plurality of the flag storing areas (F) to perform a plurality of policing judgements.
Claim 26
Dependent Claim
25 words
A usage parameter control circuit as claimed in claim 12, wherein the first pointer holding means (XP) are provided to respectively correspond to cell types.
Claim 27
Dependent Claim
24 words
A usage parameter control circuit as claimed in claim 15, wherein the counting means (CM) is provided to respectively correspond to the cell types.
Claim 28
Dependent Claim
25 words
A usage parameter control circuit as claimed in claim 20, wherein the last pointer holding means is provided to respectively correspond to the cell types.
Claim 29
Dependent Claim
24 words
A usage parameter control circuit as claimed in claim 26, wherein the first pointer holding means (XP) is included in a random access memory.
Claim 30
Dependent Claim
22 words
A usage parameter control circuit as claimed in claim 27, wherein the counting means (CM) is included in a random access memory.
Claim 31
Dependent Claim
24 words
A usage parameter control circuit as claimed in claim 28, wherein the first pointer holding means (XP) is included in a random access memory.
Claim 32
Dependent Claim
29 words
A usage parameter control circuit as claimed in claim 12, wherein the bridge memory (BM) is constructed by a random access memory which operates as a first-in first-out memory.
Claim 33
Dependent Claim
25 words
A usage parameter control circuit as claimed in claim 12, wherein the bridge memory (BM) stores a plurality of kinds of the cell type information.
Claim 34
Dependent Claim
61 words
A usage parameter control circuit as claimed in claim 12, wherein the storing capacity of the bridge memory (BM) is selected from one of a Tmax, Tmax + 1, and 2 k (where k is a natural number) that is the minimum value larger than Tmax, where Tmax is the maximum value of reference threshold time intervals of plural cell types.
Claim 35
Dependent Claim
44 words
A usage parameter control circuit as claimed in claim 22, wherein the control unit (CTL) comprises hardware error detecting means for detecting a hardware error by detecting that the count value of the counting means (CM) is negative or larger than the number n.
Claim 36
Dependent Claim
65 words
A usage parameter control circuit as claimed in claim 22, wherein the control unit (CTL) comprises hardware error detecting means for detecting a hardware error by detecting that, when the bridge memory (BM) is accessed by the first pointer holding means (XP) or the last pointer holding means (LP), the control unit (CTL) acknowledges the cell type of the cell at the accessed storing position.
Claim 37
Dependent Claim
45 words
A usage parameter control circuit as claimed in claim 35 or 36, wherein when a hardware error is detected, the control unit (CTL) resets the counting means (CM) and makes at least the flag storing areas (F) in the bridge memory (BM) to be invalid.
Claim 38
Dependent Claim
35 words
A usage parameter control circuit as claimed in claim 22, wherein the counting means (CM) is periodically reset, and at least the flag storing areas (F) in the bridge memory (BM) are periodically made invalid.
Claim 39
Dependent Claim
34 words
A usage parameter control circuit as claimed in claim 37 or 38, wherein when the counting means (CM) is reset, the policing process for arriving cells is not performed for a predetermined time period.
References Cited (Backward Citations)
No citation records indexed.
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