EP0550751A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Nonvolatile semiconductor memory

Assignee: Toshiba Corp

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Filing: 1991-09-25

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Granted: —

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Expires: 2011-09-25

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Abstract

Abstract A memory cell array is divided into a plurality of blocks. To rewrite data in a block (selected block), erroneous writing or erasing of data is prevented by applying a relaxation voltage to the source or control gate of the memory cell in the other blocks (non-selected) to relax the stress between the floating gate and the source and drain. In programming, erroneous writing of data is prevented by equalizing the source and drain of the memory cell in the non-selected block to relax the electric field between the control gate and the source and drain so that no channel current flows. To execute the negative-voltage erasure system, malfunction of a non-selected cell is prevented by equalizing the source line and data line before setting the source line and word line of the cell in the non-selected block and canceling the equalized state after erasing is executed.

Inventors

👤 Tadashi 1-7-3 Umeda Miyakawa
👤 Masamichi 45-7-308 Denenchofuhoncho Asano

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-02 11:38

CPC Classifications

G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/12; G11C16/34; G11C16/3418

Claims Analysis

Total Claims: 6

Claim 1

Independent Claim 127 words

A non-volatile semiconductor memory having a memory cell array including a plurality of non-volatile memory cells disposed in a matrix form each having a control gate, a floating gate, a source, and a drain, said memory cell array being divided into a plurality of blocks each having a plurality of said memory cells, and data in said each memory cell being alterable on the block unit basis, characterized in that: moderating potential applying means is provided at one of said control gate and said source/drain of said memory cell in a non-selected block, said moderating potential applying means moderating a potential between said floating gate and said source/drain of said memory cell in said non-selected block, during data writing to said memory cell in a selected block.

Claim 2

Dependent Claim 53 words

A non-volatile semiconductor memory according to claim 1, wherein said memory cells in said memory cell array are arranged such that said control gates constituting one row in the row direction are connected to one word line, and said drains constituting one column in the column direction are connected to one data line.

Claim 3

Dependent Claim 44 words

A non-volatile semiconductor memory according to claim 2, wherein said blocks each are constructed of an optional number of column units each having a plurality of said memory cells connected to said one data line, and said blocks are disposed in the column direction.

Claim 4

Dependent Claim 44 words

A non-volatile semiconductor memory according to claim 2, wherein said blocks each are constructed of an optional number of row units each having a plurality of said memory cells connected to said one word line, and said blocks are disposed in the row direction.

Claim 5

Dependent Claim 29 words

A non-volatile semiconductor memory according to claim 3, wherein said moderating potential applying means applies said moderating potential to said source of said memory cell in said non-selected block.

Claim 6

Dependent Claim 34 words

A non-volatile semiconductor memory according to claim 3, wherein said moderating potential applying means applies said moderating potential to said control gate of said memory cell in said non-selected block via said word line.

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