Alternate metal/source virtual ground flash EPROM cell array

Claim 1

A method of fabricating an alternate source virtual ground EPROM array in a silicon substrate of P-type conductivity, the EPROM array including a plurality of cross-point EPROM cells, the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a layer of first conductive material on the layer of first insulating material; (c) forming a layer of second insulating material on the layer of first conductive material; (d) etching selected portions of the layer of second insulating and underlying first conductive material to form a plurality of spaced-apart, parallel vertical strips of second insulating material and underlying first conductive material; (e) introducing N-type dopant into the silicon substrate regions between the parallel vertical strips of second insulating material and underlying first conductive material to form spaced-apart buried N+ bit lines; (f) introducing additional N-type dopant into alternate buried N+ bit lines to form graded source lines that alternate with buried N+ drain lines; (g) forming a plurality of spaced-apart, parallel word lines of second conductive material, said word line formed perpendicular to the vertical strips of second insulating material and underlying first conductive material and such that the second conductive material is separated from the first conductive material by the second insulating material.

Claim 5

A method of fabricating an alternate source virtual ground flash EPROM array in a silicon substrate of P-type conductivity, the EPROM array including a plurality of cross-point EPROM cells, the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a first layer of polysilicon (poly 1) on the layer of first insulating material; (c) forming a layer of second insulating material on the first layer of poly 1; (d) forming a poly 1 mask to define parallel lines of the second insulating material and underlying first layer of poly 1; (e) etching exposed portions of the second insulating material and underlying first layer of poly 1 to define a plurality of spaced-apart, parallel vertical strips of second insulating material and underlying poly 1; (f) after removing the poly 1 mask, introducing N-type dopant into the silicon substrate between the parallel vertical strips of second insulating material and underlying poly 1 to form spaced-apart, parallel N+ bit lines; (g) implanting alternate N+ bit lines with additional N+ dopant to form graded source lines that alternate with buried N+ drain lines; (h) performing a differential oxidation step to form additional oxide on the second insulating material of the vertical strips while simultaneously forming oxide over the graded source lines and the N+ drain lines; (i) forming a second layer of polysilicon (poly 2) over the structure formed in steps (a) - (h) above; (j) forming a layer of tungsten silicide over the second layer of poly 2; (k) forming a poly 2 mask on the layer of tungsten silicide; (l) etching the tungsten silicide and the underlying poly 2 to form poly 2 word lines perpendicular to the strips of second insulating material and underlying poly 1 but separated from the poly 1 by the second insulating material; and (m) utilizing the poly 2 word lines in a stacked etch step to define poly 1 floating gates of the cross-point EPROM cells of the array.