EP0560020A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Digital signal processing function appearing as hardware FIFO
Assignee: International Business Machines Corp
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Filing: 1993-01-18
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Granted: —
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Expires: 2013-01-18
Abstract
Abstract A means of making a digital signal processing function perform independently of the system processor and appear as a hardware FIFO. The architecture of the present invention comprises a digital signal processing means connected between the data output of a first FIFO buffer and the data input of a second FIFO buffer, a control means for controlling the digital signal processing means as a function of the presence and absence of data in the first FIFO buffer and said second FIFO buffer and control signals received from a source of control signals. Data throughput is performed asynchronously and independently of the system environment and comprises the following steps: receiving data on the data input of the first FIFO buffer, transferring that data to the digital signal processor, processing the data, then transferring the processed data to the second FIFO buffer to be output when the data receiver is ready to accept to data.
Inventors
- 👤 Steve Harris Weingart
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 21:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879; G06F5/00; G06F5/06; G06F9/3824
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
104 words
A processing system, comprising: a first first-in-first-out (FIFO) buffer having a first storage area, a first data input and a first data output; a second FIFO buffer having a second storage area, a second data input and a second data output; digital signal processing means connected between said first data output of said first FIFO buffer and said second data input of said second FIFO buffer; and control means for controlling said digital signal processing means as a function of the presence and absence of data in said first storage area of first FIFO buffer and said second storage area of second FIFO buffer.
Claim 2
Dependent Claim
48 words
The processing system of claim 1, wherein said first FIFO buffer further comprises: a first buffer full indicator output for indicating a first FIFO buffer full condition; and a first buffer write input for enabling said first FIFO buffer to receive input data at said first data input.
Claim 3
Dependent Claim
47 words
The processing system of claim 2, wherein said first FIFO buffer further comprises: a first buffer empty indicator output for indicating a first FIFO buffer empty condition; and a first buffer read input for enabling said first FIFO buffer to output data at said first data output.
Claim 4
Dependent Claim
73 words
The processing system of claim 3, wherein said control means further comprises: an input coupled to said first buffer empty indicator output of said first FIFO buffer; an output coupled to said first buffer read input of said first FIFO buffer; and means for controlling the output of data from said first FIFO buffer to said digital signal processing means as a function of control signals received from a source of control signals.
Claim 5
Dependent Claim
85 words
The processing system of claim 4, wherein said digital signal processing means comprises: a third data input coupled to said first data output of said first FIFO buffer; a third data output coupled to said second data input of said second FIFO buffer; a control signal input coupled to an output of said control means for receiving control signals from said control means; and means for processing data output from said first FIFO buffer as a function of control signals received from said control means.
Claim 6
Dependent Claim
47 words
The processing system of claim 5, wherein said second FIFO buffer further comprises: a second buffer empty indicator output for indicating a second FIFO buffer empty condition; and a second buffer read input for enabling said second FIFO buffer to output data at said second data output.
Claim 7
Dependent Claim
48 words
The processing system of claim 6, wherein said second FIFO buffer further comprises: a second buffer full indicator output for indicating a second FIFO buffer full condition; and a second buffer write input for enabling said second FIFO buffer to receive input data at said second data input.
Claim 8
Dependent Claim
73 words
The processing system of claim 7, wherein said control means further comprises: an input coupled to said second buffer full indicator output of said second FIFO buffer; an output coupled to said second buffer write input of said second FIFO buffer; and means for controlling the output of data from said digital signal processing means to said second FIFO buffer as a function of control signals received from a source of control signals.
Claim 9
Dependent Claim
15 words
The processing system of claim 8, wherein said control means comprises a finite state machine.
Claim 10
Dependent Claim
47 words
The processing system of claim 1, wherein said second FIFO buffer further comprises: a second buffer empty indicator output for indicating a second FIFO buffer empty condition; and a second buffer read input for enabling said second FIFO buffer to output data at said second data output.
Claim 11
Dependent Claim
48 words
The processing system of claim 10, wherein said second FIFO buffer further comprises: a second buffer full indicator output for indicating a second FIFO buffer full condition; and a second buffer write input for enabling said second FIFO buffer to receive input data at said second data input.
Claim 12
Dependent Claim
73 words
The processing system of claim 11, wherein said control means further comprises: an input coupled to said second buffer full indicator output of said second FIFO buffer; an output coupled to said second buffer write input of said second FIFO buffer; and means for controlling the output of data from said digital signal processing means to said second FIFO buffer as a function of control signals received from a source of control signals.
Claim 13
Dependent Claim
85 words
The processing system of claim 1, wherein said digital signal processing means comprises: a third data input coupled to said first data output of said first FIFO buffer; a third data output coupled to said second data input of said second FIFO buffer; a control signal input coupled to an output of said control means for receiving control signals from said control means; and means for processing data output from said first FIFO buffer as a function of control signals received from said control means.
Claim 14
Dependent Claim
19 words
The processing system of claim 13, wherein said digital signal processing means comprises a data encoding and/or decoding means.
Claim 15
Dependent Claim
20 words
The processing system of claim 13, wherein said digital signal processing means comprises an audio and/or video signal processing means.
Claim 16
Dependent Claim
20 words
The processing system of claim 13, wherein said digital signal processing means comprises an instrumentation or sensing signal processing means.
Claim 17
Dependent Claim
19 words
The processing system of claim 13, wherein said digital signal processing means comprises an data translation or substitution means.
Claim 18
Independent Claim
131 words
A method for controlling the data throughput of a digital signal processing system, comprising the steps of: receiving data on a first data input of a first first-in-first-out (FIFO) buffer; transferring data from said first FIFO buffer to a digital signal processing means as a function of control signals received from a source of control signals; processing data transferred from said first FIFO buffer to said digital signal processing means as a function of control signals received from a source of control signals; transferring processed data from said digital signal processing means to a second FIFO buffer as a function of control signals received from a source of control signals; and outputing data from said second FIFO buffer as a function of control signals received from a source of control signals.
Claim 19
Dependent Claim
95 words
The method of claim 18, wherein said data receiving step further comprises the steps of: outputing a first FIFO buffer empty indication; outputing a first FIFO buffer not full indication; receiving a first FIFO write indication, wherein said write indication enables said first FIFO buffer to input data on said first data input; receiving data on said first data input of said first FIFO buffer; storing data in said first FIFO; outputing a first FIFO buffer not empty indication; and outputing a first FIFO buffer full indication if said first FIFO completely fills with data.
Claim 20
Dependent Claim
86 words
The method of claim 18, wherein said data transfer step from said first FIFO buffer further comprises the steps of: receiving a first FIFO buffer read indication, wherein said read indication enables said first FIFO buffer to output data on said first data output; transferring data from said first FIFO buffer to said digital signal processing means; and ceasing the transfer of data from said first FIFO buffer to said digital signal processor if said first FIFO does not receive a first FIFO buffer read indication.
Claim 21
Dependent Claim
103 words
The method of claim 18, wherein said data transferring step from said digital signal processing means further comprises the steps of: outputing a second FIFO buffer empty indication; outputing a second FIFO buffer not full indication; receiving a second FIFO write indication, wherein said write indication enables said second FIFO buffer to input data in a second data input; receiving data on said second data input of said second FIFO buffer; storing data in said second FIFO; outputing a second FIFO buffer not empty indication; and outputing a second FIFO buffer full indication if said second FIFO buffer becomes completely full with data.
Claim 22
Dependent Claim
77 words
The method of claim 18, wherein said data outputing step further comprises the steps of: receiving a second FIFO buffer read indication, wherein said read indication enables second FIFO buffer to transfer data to output data on said second data output; transferring data from said second FIFO buffer on said second data output; and ceasing the transfer of data from said second FIFO buffer if said second FIFO does not receive a second FIFO buffer read indication.
References Cited (Backward Citations)
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