Device and method for data compression/decompression

Claim 2

A method as claimed in claim 1 wherein a first data value of the sequence of transformed image data values is an output of the first digital filter and wherein a second data value of the sequence of transformed image data values is an output of the second digital filter.

Claim 3

A method as claimed in claim 1 or 2 wherein the first digital filter is a boundary filter.

Claim 5

A method as claimed in claim 4 wherein each of the first, second, third and fourth accumulators comprises at least an adder circuit and a storage circuit, each of the storage circuits storing a number A of partially transformed data values during processing of one octave of a decomposition, and each of the storage circuits storing a number B of partially transformed data values during processing of another octave of a decomposition, wherein A is not equal to B.

Claim 6

A method as claimed in claim 4 or 5 wherein the sequence of data values comprises data values of rows and columns of a two-dimensional image, the method transforming both the rows and the columns of data values into a sub-band decomposition.

Claim 8

A method as claimed in claim 7 wherein the output of the second accumulator is supplied to a second input of the first accumulator, wherein the output of the third accumulator is supplied to a third input of the second accumulator, and wherein the output of the fourth accumulator is supplied to a third input of the third accumulator.

Claim 11

A wavelet transform circuit arranged for transforming a sequence of a number C of input image data values adjacent an image boundary into a corresponding sequence of the number C of transformed image data values, the transformed image data values consisting of alternating low and high pass transformed image data values.

Claim 12

A wavelet transform circuit for transforming a sequence of data values adjacent a boundary of the data values, the sequence comprising a boundary subsequence adjacent the boundary and a non-boundary subsequence, the circuit comprising: a multiplier circuit having an input for receiving an input data value and a plurality outputs; a first multiplexer having a plurality of data inputs each coupled to selected ones of the plurality of outputs of the multiplier circuit, at least one control input, and a data output, a first accumulator circuit having a first data input coupled to the data output of the first multiplexer, a second data input, a plurality of control inputs, and a data output, a second multiplexer having a plurality of data inputs each coupled to selected ones of the plurality of outputs of the multiplier circuit, at least one control input, and a data output, a second accumulator circuit having a first data input coupled to the data output of the second multiplexer, a second data input coupled to the data output of the first accumulator circuit, a third data input, a plurality of control inputs, and a data output, a third multiplexer having a plurality of data inputs, at least one control input, and a data output; a third accumulator circuit having a first data input coupled to the data output of the third multiplexer, a second data input coupled to the data output of the second accumulator circuit, a third data input, a plurality of control inputs, and a data output, a fourth accumulator circuit having a first data input, a second data input coupled to one of the plurality of outputs of the multiplier circuit, a plurality of control inputs, and a data output coupled to the third data input of the third accumulator circuit, and a control circuit coupled to the control inputs of the first, second and third multiplexers and the first, second, third and fourth accumulator circuits, the control circuit controlling the first, second, third multiplexers and the first, second, third and fourth accumulator circuits to transform the boundary subsequence using a first digital filter and to transform the non-boundary subsequence using a second digital filter.

Claim 14

A method as claimed in claim 13 wherein the step of addressing a sequence comprises adding one of a first value and a second value to a first address to generate a second address, the first and second addresses of the sequence being addresses of successive ones of the sequence of memory locations, and wherein the step of addressing a subsequence comprises the step of adding one of a third value and a fourth value to a first address of the subsequence of memory locations to generate a second address of the subsequence of memory locations, the first and second addresses of the subsequence being addresses of successive ones of the subsequence of memory locations.

Claim 15

A method as claimed in claim 13 wherein the step of addressing a sequence comprises subtracting one of a first value and a second value from a first address to generate a second address, the first and second addresses of the sequence being addresses of successive ones of the sequence of memory locations, and wherein the step of addressing a subsequence comprises the step of subtracting one of a third value and a fourth value from a first address of the subsequence of memory locations to generate a second address of the subsequence of memory locations, the first and second addresses of the subsequence being addresses of successive ones of the subsequence of memory locations.

Claim 17

A circuit for generating an address of a memory location of a plurality of memory locations storing a plurality of data values of a sub-band decomposition, the circuit comprising: a first counter which increments by an octave-dependent first variable number of counts, a multiplier circuit having a first data input coupled to an output of the first counter, a second data input coupled to receive a value indicative of a size of an image, and a data output, a second counter which increments by an octave-dependent second variable number of counts, an adder circuit having a first data input coupled to the out-put of the multiplier circuit, a second data input coupled to an output of the second counter, and a data output on which the address is generated.

Claim 18

A circuit as claimed in claim 17 wherein the first counter receives a clock input signal and increments by the first variable number of counts in one clock cycle of the clock input signal, and wherein the second counter receives a clock input signal and increments by the second variable number of counts in one clock cycle of the clock input signal.

Claim 19

A state machine for generating an address of a memory location of a plurality of memory locations storing a plurality of data values of a sub-band decomposition, the data values comprising luminance data values, the state machine receiving: a first signal upon which the state machine changes states, a second signal indicative of an octave of the sub-band decomposition, and a third signal indicative of a whether the address being generated is a luminance data value, the state machine changing state based upon the first, second, and third signals.

Claim 20

A state machine as claimed in claim 19 wherein the state machine also receives a fourth signal indicative of a whether the address being generated is a chrominance data value, the state machine changing state based upon the fourth signal.

Claim 21

A circuit for generating an address and comprising: an accumulator circuit having a first data input for receiving a first increment value, a second data input for receiving a second increment value, a third data input, and a data output, said accumulator circuit, and a storage element having a data input coupled to the data output of the accumulator circuit, and a data output coupled to the third data input of the accumulator circuit, the address being output on the data output of the storage element.

Claim 22

a circuit as claimed in claim 22 wherein the accumulator circuit has a fourth data input receiving an address base-offset chrominance value, and a fifth data input receiving an address base-offset luminance value.

Claim 23

A circuit comprising: a flag generating circuit which receives a plurality of data values of a new block and a plurality of data values of an old block and generates a plurality of different flags, the new block being a block of a sub-band composition of a new frame, the old block being a block of a sub-band decomposition of an old frame, the different flags being selected from flags consisting of ORIGIN, NEW_Z, NO_Z, MOTION, NOFLAG; and a stage machine which assumes a given new state based on a current stage of the state machine and also on the different flags, the state machine outputting a token indicating the new state of the stage machine, the new stage being selected from VOID, SEND, STILL, SEND-STILL, STOP.

Claim 25

A method as claimed in claim 24 wherein the digital circuit is a low pass forward transform perfect reconstruction digital filter.

Claim 26

A method as claimed in claim 26 wherein the digital circuit comprises a convolver.

Claim 28

A method as claimed in claim 28 wherein the rows of memory locations read in the reading step are different rows from the rows of memory locations written in the writing step or are the same rows of memory locations that are written in the writing step.

Claim 29

A method as claimed in claim 27 or 28 wherein the number of first data values equal the number of second data values.

Claim 30

A method as claimed in claim 27, 28 or 28 wherein the memory is a dynamic memory.

Claim 33

A method as claimed in claim 32 wherein the second memory is a plurality of static random access memory locations, and wherein the fourth memory is another plurality of static random access memory locations.

Claim 34

A method as claimed in claim 32 or 33 wherein the first block of low pass component data values and associated first high pass component trees of blocks of data values consist of 256 memory locations, and wherein the first block of low pass component data values and associated first high pass component trees of blocks of data values comprise a part of a three octave sub-band decomposition.

Claim 35

A method as claimed in claim 32, 33 or 34 wherein the processing step generates a third block of low pass component data values and associated third high pass component trees of blocks of data values, the method comprising the steps of: writing the third block of low pass component data values and associated third high pass component trees of blocks of data values into the fourth memory; reading a fourth block of low pass component data values and associated fourth high pass component trees of blocks of data values from the second plurality of dynamic memory locations, the dynamic memory locations from which the fourth block is read being different dynamic memory locations from the dynamic memory locations from which said second block was read; and after the step of reading the fourth block, writing the third block of low pass component data values and associated third high pass component trees of blocks of data values into the second plurality of dynamic memory locations.

Claim 36

A method as claimed in claim 32, 33 or 34 wherein the processing step generates a third block of low pass component data values and associated third high pass component trees of blocks of data values, the method comprising the steps of: writing the third block of low pass component data values and associated third high pass component trees of blocks of data values into the fourth memory, and reading the third block of low pass component data values and associated third high pass component trees of blocks of data values from the fourth memory and writing the third block of low pass component data values and associated third high pass component trees of blocks of data values into the second plurality of dynamic memory locations.

Claim 40

A system as claimed in claim 30 wherein the first circuit comprises: means for generating a mode control signal from the input data stream, quantizer means for receiving the transformed image data values of the input data stream and the mode control signal and for quantizing said transformed image data values into the quantized data stream using one of a first quantization method and a second quantization method depending on the mode control signal, the quantizer means also being for generating the inverse quantized data stream from the quantized data stream, and means for generating a compressed data stream from the quantized data stream, wherein the second circuit comprises: means for generating a mode control signal from the compressed data stream, means for generating quantized data values from the compressed data stream, and quantizer means for receiving said quantized data values of the compressed data stream and the mode control signal and for inverse quantizing the quantized data values into a data stream.

Claim 41

A circuit for generating an address for traversing a sub-band decomposition, the circuit comprising: a first counter receiving a first count enable signal, and generating a first plurality of count output signals and a first carry out signal, a second counter receiving a second count enable signal, and generating a second plurality of count output signals and a second carry out signal, a third counter receiving a third count enable signal, and generating a third plurality of count output signals and a third carry out signal, a fourth counter receiving a fourth count enable signal and generating a fourth plurality of counter output signals and a fourth carry out signal, and means for receiving the first, second, third, and fourth carry out signals and for generating the first, second, third and fourth count enable signals, the first, second, third and fourth plurality of count output signals comprising the address.

Claim 42

A circuit as claimed in claim 41 wherein the sub-band decomposition comprises three high pass sub-bands, and wherein the first plurality of count output signals is indicative of an X address of a root of a tree, the second plurality of count output signals is indicative of a Y address of the root of the tree, the tree comprises a plurality of blocks of data values, the third plurality of count output signals is indicative of an address of data values in a block of data values of the tree, and the fourth plurality of counter output signals is indicative of the sub-band of the tree.