EP0644548A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated memory cube, structure and fabrication
Assignee: International Business Machines Corp
•
Filing: 1994-09-02
•
Granted: —
•
Expires: 2014-09-02
Abstract
Abstract An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N × M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
Inventors
- 👤 Claude Louis Bertin
- 👤 Wayne John Howell
- 👤 Erik Leigh Hedberg
- 👤 Howard Leo Kalter
- 👤 Gordon Arthur Kelley Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 13:07
CPC Classifications
H; H10; H10W; H10W90/00; G; G11; G11C; G11C5/00; G11C5/06; H10W72/00; H10W72/834; H10W90/20; H10W90/22; H10W90/284; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
195 words
An integrated memory cube which emulates a single memory chip architecture, said integrated memory cube comprising: a combination memory chip and logic chip stack including (i) N memory chips (wherein N ≧ 2) each having M memory devices (wherein M ≧ 2), along with two substantially parallel planar main surfaces and an edge surface, (ii) a logic chip electrically connected to each of the N memory chips for coordinating external communication with the N memory chips of the stack, said logic chip also having two parallel planar main surfaces and an edge surface, and (iii) at least one planar main surface of each chip in t the stack being coupled to a planar main surface of an adjacent chip in the stack, the edge surfaces of the N memory chips and the edge surface of the logic chip aligning to form at least one side surface of the stack, said stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack, said electrically connected logic chip and N memory chips having an integrated memory architecture to emulate single memory chip structure with N × M memory devices.
Claim 2
Dependent Claim
66 words
The integrated memory cube of claim 1, wherein one of said two parallel planar main surfaces of said logic chip comprises an upper surface of the logic chip, and wherein said upper surface of the logic chip includes an array of contact pads, at least some of said contact pads of said array of contact pads comprising I/O contacts for external circuitry connection to the stack.
Claim 3
Dependent Claim
35 words
The integrated memory cube of claim 2, wherein the logic chip is disposed at an end of the stack such that the upper surface of the logic chip comprises the end surface of the stack.
Claim 4
Dependent Claim
51 words
The integrated memory cube of claim 3, further comprising a lead frame secured to the stack adjacent its end surface, said lead frame having an inner opening extending therethrough such that at least a portion of the array of contact pads on the upper surface of the logic chip remains exposed.
Claim 5
Dependent Claim
39 words
The integrated memory cube of claim 4, further comprising conventional wirebonding electrically connecting the lead frame and at least some of the exposed contact pads of the array of contact pads on the upper surface of the logic chip.
Claim 6
Dependent Claim
80 words
The integrated memory cube of claim 3, further comprising a spacer layer disposed on the end surface of the stack, said spacer layer having an inner opening extending therethrough and sized to expose at least a portion of the contact pads on the upper surface of the logic chip, said spacer layer having a thickness sufficient to allow formation of T-connects along the at least one side surface of the stack adjacent to the upper surface of the logic chip.
Claim 7
Dependent Claim
49 words
The integrated memory cube of claim 6, further comprising a lead frame secured to on exposed surface of the spacer layer, said lead frame also having an inner opening extending therethrough sized such that the contact pads exposed through the spacer layer are also exposed through the lead frame.
Claim 8
Dependent Claim
33 words
The integrated memory cube of claim 7, further comprising conventional wirebonding electrically connecting the lead frame and at least some of the exposed contact pads on the upper surface of the logic chip.
Claim 9
Dependent Claim
28 words
The integrated memory cube of claim 2, wherein at least two of said contact pads of said array of contact pads are electrically interconnected for logic function programming.
Claim 10
Dependent Claim
39 words
The integrated memory cube of claim 1, wherein the logic chip includes logic means for holding each of said N memory chips of the stack in a sleep mode in response to a control command received from external circuitry.
Claim 11
Dependent Claim
56 words
The integrated memory cube of claim 1, wherein the logic chip is electrically connected to receive an address signal from external circuitry and wherein the logic chip includes logic means for decoding the address signal to identify at least one memory chip of the N memory chips having a memory device addressed by the address signal.
Claim 12
Dependent Claim
26 words
The integrated memory cube of claim 1, wherein the logic chip includes logic means for sequentially refreshing each of the N memory chips in the stack.
Claim 13
Dependent Claim
36 words
The integrated memory cube of claim 12, wherein the logic means for sequentially refreshing includes a counter connected to sequentially track which memory chip of said N memory chips in the stack is to be refreshed.
Claim 14
Dependent Claim
29 words
The integrated memory cube of claim 1, wherein the logic chip includes logic means for regulating a received voltage to an on-chip voltage for powering at a desired level.
Claim 15
Dependent Claim
11 words
The integrated memory cube of claim 1, wherein N equals four.
Claim 16
Dependent Claim
17 words
The integrated memory cube of claim 1, wherein the N memory chips each comprise a RAM chip.
Claim 17
Dependent Claim
58 words
The integrated memory cube of claim 1, wherein at least some of the N memory chips include transfer metallurgy extending to the at least one side surface of the stack, and wherein the integrated memory cube further comprises a metallization pattern disposed on the stack's at least one side surface and electrically connecting the transfer metallurgy extending thereto.
Claim 18
Dependent Claim
39 words
The integrated memory cube of claim 17, wherein the metallization pattern disposed on the stack's at least one side surface electrically connects with the transfer metallurgy extending to the at least one side surface of the stack via T-connects.
Claim 19
Dependent Claim
112 words
The integrated memory cube of claim 18, wherein the logic chip is disposed adjacent to the end surface of said stack and includes transfer metallurgy extending to the at least one side surface of the stack, and wherein the integrated memory cube further comprises a spacer layer covering the logic chip and having an edge aligned with the at least one side surface of the stack, the spacer layer having a width and thickness sufficient to allow T-connects between the transfer metallurgy on the logic chip extending to the at least one side surface of the stack and the metallization pattern disposed on the at least one side surface of the stack.
Claim 20
Independent Claim
210 words
A method for fabricating an integrated memory cube which emulates a single memory chip architecture, said fabricating method comprising the steps of: (a) providing N memory chips (wherein N ≧ 2) each having M memory devices (wherein M ≧ 2), along with two substantially parallel planar main surfaces and an edge surface; (b) providing a logic chip having two substantially parallel planar main surfaces and an edge surface; (c) forming a stack by securing the N memory chips and the logic chip together such that at least one planar main surface of each chip in the stack is coupled to a planar main surface of an adjacent chip in the stack, and such that the edge surfaces of the memory chips and the edge surface of the logic chip align to form at least one side surface of the stack, the stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack; and (d) electrically interconnecting the logic chip and the N memory chips, said logic chip coordinating external communication with the N memory chips of the stack so that an integrated memory structure exists which emulates the functional characteristics of a single memory chip structure with N × M memory devices.
Claim 21
Dependent Claim
38 words
The fabricating method of claim 20, wherein the electrical interconnecting step (d) includes disposing a metallization pattern on the at least one side surface of the stack to electrically interconnect the logic chip and the N memory chips.
Claim 22
Dependent Claim
87 words
The fabricating method of claim 21, wherein each of the N memory chips and the logic chip provided in said steps (a) & (b), respectively, include transfer metallization extending to the at least one side surface of the stack, and wherein the electrical interconnecting step (d) further includes the step of forming T-connects along at least one side surface of the stack to electrically interconnect the metallization pattern with at least some of the transfer metallurgies extending to the at least one side surface of the stack.
Claim 23
Dependent Claim
94 words
The fabricating method of claim 22, wherein said stack forming step (c) includes forming the stack such that the logic chip comprises an end chip in the stack adjacent to the end surface of the stack, and wherein said fabricating method further comprises the step of disposing a spacer layer on the end surface of the stack so that the electrical connecting step (d) includes electrically connecting the stack's side surface metallization pattern to the transfer metallurgy extending from the logic chip to the at least one side surface of the stack using T-connects.
Claim 24
Dependent Claim
96 words
The fabricating method of claim 23, wherein said providing step (b) includes providing a logic chip having an upper surface with an array of contact pads disposed thereon, and further comprising the step of preforming the spacer layer disposed on the end surface of the stack, said preforming of the spacer layer including providing an inner opening extending through the spacer layer such that when the spacer layer is disposed on the end surface of the stack at least some of the array of contact pads on the upper surface of the logic chip remain exposed.
Claim 25
Dependent Claim
44 words
The fabricating method of claim 24, further comprising the step of securing a lead frame to an exposed surface of the spacer layer, the lead frame having an inner opening extending therethrough such that the contact pads exposed through the spacer layer remain exposed.
Claim 26
Dependent Claim
37 words
The fabricating method of claim 25, wherein said electrical interconnecting step (d) includes forming conventional wirebonds between at least some of the exposed contact pads on the upper surface of the logic chip and the lead frame.
Claim 27
Dependent Claim
192 words
The fabricating method of claim 21, wherein said step of disposing a metallization pattern on the at least one side surface of the stack includes the steps of: forming multiple stacks, each stack having N memory chips and a logic chip secured together such that a planar main surface of each chip in the stack is coupled to a planar main surface of an adjacent chip in the stack, each stack having an end surface and at least one side surface; forming an extended stack of the multiple stacks by disposing a segmentation material between the end surfaces of adjacent stacks in the extended stack, said segmentation material being removable upon applying of a predefined treatment to the extended stack, said extended stack being formed such that the at least one side surfaces of the multiple stacks align in a common plane; forming a metallization pattern on the at least one side surfaces of the multiple stacks in the extended stack; and disassembling the extended stack by applying the predefined treatment to the extended stack such the segmentation material is removed, thereby separating the multiple stacks with the metallization patterns disposed thereon.
Claim 28
Dependent Claim
25 words
The fabricating method of claim 27, wherein the extended stack forming step includes placing parylene between end surfaces of adjacent stacks in the extended stack.
Claim 29
Dependent Claim
31 words
The fabricating method of claim 20, further comprising the step of testing and burning-in each of the N memory chips and the logic chip prior to said stack forming step (c).
Claim 30
Dependent Claim
32 words
The fabricating method of claim 20, further comprising the step of providing and electrically connecting I/O leads to the logic chip and encapsulating the stack such that said I/O leads extend therefrom.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.