EP0645723A2
Expired / Lapsed
EP
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A system for synthesizing field programmable gate array implementations from high level circuit description
Assignee: AT&T Inc
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Filing: 1994-09-14
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Granted: —
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Expires: 2014-09-14
Abstract
Abstract A system is disclosed for synthesizing field programmable gate array (FPGA) implementations from high level circuit descriptions. A designer may describe circuits using a textual language or a graphics tool. The system will compile such circuit descriptions into technology mapped descriptions for use with FPGA's. The system will support both random logic circuits and data path circuits. The system uses advanced optimization techniques to produce efficient FPGA implementations. Thus, the system produces high quality results while providing users with a high level of abstraction in design, and thus frees the user from architectural details of the target FPGA. <IMAGE>
Inventors
- 👤 Michael R. Cantone
- 👤 Nam-Sung Woo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 04:03
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; G06F30/347
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
90 words
A system for synthesizing circuits from a high level description in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising: a computer processor; a display monitor connected to the computer processor; textual data entry means connected to the computer processor for allowing the entry of a textual language describing a plurality of electronic circuit elements in terms of parameterized modules; and means for compiling said textual language into field programmable gate array configuration data.
Claim 2
Dependent Claim
21 words
The system of claim 1 where in said electronic circuit elements comprise: random logic circuit elements and data path circuit elements.
Claim 3
Dependent Claim
50 words
The system of claim 1 further comprising: means for receiving a parameterized memory module described in said textual language specifying initial contents of said memory module; and means for generating a field programmable gate array configuration in which the contents of a memory unit are the said specified initial contents.
Claim 4
Dependent Claim
53 words
The system of claim 1 further comprising: means for receiving a parameterized module described in said textual language specifying whether optimization is to be based on performance or area; and means for optimizing the field programmable gate array configuration of said module based upon performance or area depending on said textual language specification.
Claim 5
Dependent Claim
48 words
The system of claim 1 wherein said field programmable gate array configuration data further comprises: information identifying certain programmable logic cells as a group such that said identified group of programmable logic cells will be implemented in relative proximity to each other in the field programmable gate array.
Claim 6
Independent Claim
132 words
A system of optimizing a circuit implementation in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising: a computer processor; means for receiving a description of a first electronic circuit design module specifying an output signal and a polarity of said output signal, and a second electronic circuit design module specifying an input signal and a polarity of said input signal, said output signal of the first module corresponding to the input signal of said second module; and means for reversing the signal polarities of said input signal and said output signal to reduce the number of programmable logic cells required to implement said first module and said second module in the field programmable gate array.
Claim 7
Independent Claim
119 words
A system for synthesizing a circuit implementation in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising: a computer processor; means for receiving a textual description of a first electronic circuit design element connected to a second electronic circuit design element; means for implementing said first electronic circuit design element and said second electronic circuit design element in at least one programmable logic cell such that the output of said first electronic circuit design element is connected to said second electronic circuit design element; and means for optimizing the field programmable gate array implementation of said first and second electronic circuit design elements.
Claim 8
Dependent Claim
39 words
The system of claim 7 wherein said means for optimizing comprises: means for implementing said first and second electronic circuit design elements in at least one programmable logic cell so as to minimize the number of programmable logic cells.
Claim 9
Dependent Claim
38 words
The system of claim 7 wherein said means for optimizing comprises: means for implementing said first and second electronic circuit design elements in at least one programmable logic cell so as to minimize the timing of said implementation.
Claim 10
Dependent Claim
32 words
The system of claim 7 wherein said means for optimizing comprises: means for implementing said first electronic circuit design element and said second electronic circuit design element in one programmable logic cell.
Claim 11
Independent Claim
178 words
A system for synthesizing a circuit from a high level circuit description in a field programmable gate array comprising: a computer processor; a graphical display monitor connected to the computer processor for the display of graphical information; a graphical data entry device connected to the computer processor; means for displaying a plurality of icons representative of a plurality of pre-defined electronic circuit elements in a first section of said graphical display monitor, said elements comprising random logic circuit elements and data path circuit elements; means for choosing one of said electronic circuit elements by choosing its representative icon and for positioning said chosen icon in a second area of said graphical display monitor; means for assigning attributes to said electronic circuit elements which are represented by said icons in said second area of said graphical display monitor; means for generating a textual description of said electronic circuit elements in terms of parameterized modules from said chosen icons and assigned attributes; and means for compiling said textual description of electronic circuit elements into field programmable gate array configuration data.
Claim 12
Dependent Claim
23 words
The system of claim 1 or 11 wherein said field programmable gate array configuration data is a field programmable gate array application netlist.
Claim 13
Dependent Claim
95 words
The system of claim 11 further composing: means for defining a macro as a set of pre-defined electronic circuit elements; means for assigning certain attributes of said pre-defined electronic circuit elements and identifying said attributes as constants; means for identifying certain attributes of said pre-defined electronic circuit elements as variable; means for displaying an icon, representative of said macro and displaying said icon in said first section of the graphical display monitor for use as a pre-defined circuit element; and means for assigning said variable attributes if said macro is chosen as a design element.
Claim 14
Dependent Claim
76 words
The system of claim 11 further comprising means for defining a derived element, said means comprising: means for choosing one of said plurality of icons representative of a pre-defined electronic circuit element; means for assigning certain attributes of said pre-defined electronic circuit element and identifying said attributes as constants; and means for displaying an icon, representative of said derived element in said first section of the graphical display monitor for use as a pre-defined circuit element.
Claim 15
Independent Claim
69 words
A method for synthesizing a circuit from a high level circuit description in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the method comprising the steps of: describing a plurality of electronic circuit elements in terms of parameterized modules using a textual language; and compiling said textual language into field programmable gate array configuration data.
Claim 16
Dependent Claim
20 words
The method of claim 15 wherein said electronic circuit elements comprise: random logic circuit elements and data path circuit elements.
Claim 17
Dependent Claim
47 words
The method of claim 15 further comprising the steps of: describing a parameterized memory module in said textual language specifying initial contents of said memory module; and implementing a field programmable gate array in which the contents of a memory unit are the said specified initial contents.
Claim 18
Dependent Claim
51 words
The method of claim 15 further comprising the steps of: describing a parameterized module in said textual language specifying whether optimization is to be based on performance or area; and optimizing the field programmable gate array configuration of said module based upon performance or area depending on said textual language specification.
Claim 19
Dependent Claim
48 words
The method of claim 15, wherein said field programmable gate array configuration data further comprises: information identifying certain programmable logic cells as a group such that said identified group of programmable logic cells will be implemented in relative proximity to each other in the field programmable gate array.
Claim 20
Independent Claim
125 words
A method for optimizing a field programmable gate array configuration, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the method comprising the steps of receiving a description of a first electronic circuit design module specifying an output signal and a polarity of said output signal, and a second electronic circuit design module specifying an input signal and a polarity of said input signal, said output signal of the first module corresponding to the input signal of said second module; and reversing the signal polarities of said input signal and said output signal to reduce the number of programmable logic cells required to implement said first module and said second module in the field programmable gate array.
Claim 21
Independent Claim
113 words
A method for synthesizing a circuit implementation in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the method comprising the steps of: receiving a textual description of a first electronic circuit design element connected to a second electronic circuit design element; implementing said first electronic circuit design element and said second electronic circuit design element in at least one programmable logic cell such that the output of said first electronic circuit design element is connected to said second electronic circuit design element; and optimizing the field programmable gate array implementation of said first and second electronic circuit design elements.
Claim 22
Dependent Claim
41 words
The method of claim 21 wherein said step of optimizing further comprises the step of: implementing said first and second electronic circuit design elements in at least one programmable logic cell so as to minimize the number of programmable logic cells.
Claim 23
Dependent Claim
40 words
The method of claim 21 wherein said step of optimizing further comprises the step of: implementing said first and second electronic circuit design elements in at least one programmable logic cell so as to minimize the timing of said implementation.
Claim 24
Dependent Claim
34 words
The method of claim 21 wherein said step of optimizing further comprises the step of: implementing said first electronic circuit design element and said second electronic circuit design element in one programmable logic cell
Claim 25
Independent Claim
143 words
A method for synthesizing programmable gate array implementations from high level circuit descriptions comprising the steps of displaying a plurality of icons representative of a plurality of pre-defined electronic circuit design elements in a first section of a graphical display monitor, said design elements comprising random logic circuit elements and data path circuit elements; choosing one of said electronic circuit design elements by choosing its representative icon and for positioning said chosen icon in a second area of said graphical display monitor; assignment attributes to said electronic circuit design elements which are represented by said icons in said second area of said graphical display monitor; generating a textual description of said electronic circuit design elements in terms of parameterized modules from said chosen icons and assigned attributes; and compiling said textual description of electronic circuit elements into field programmable gate array configuration data.
Claim 26
Dependent Claim
23 words
The method of claim 15 or 25 wherein said field programmable gate array configuration data is a field programmable gate array application netlist.
Claim 27
Dependent Claim
93 words
The method of claim 25 further comprising the steps of: defining a macro as a set of pre-defined electronic circuit design elements; assigning certain attributes of said pre-defined electronic circuit design elements and identifying said attributes a constants; identifying certain attributes of said pre-defined electronic circuit design elements as variable; displaying an icon, representative of said macro and displaying said icon in said first section of the graphical display monitor, for use as a pre-defined circuit design element; and assigning said variable attributes if said macro is chosen as a circuit design element.
Claim 28
Dependent Claim
73 words
The method of claim 25 further comprising steps for defining a derived element, said steps comprising: choosing one of said plurality of icons representative of a pre-defined electronic circuit design element; assigning certain attributes of said pre-defined electronic circuit design element and identifying said attributes as constants; and displaying an icon, representative of said derived element in said first section of the graphical display monitor for use as a pre-defined circuit design element.
References Cited (Backward Citations)
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