Decoder for compressed and multiplexed video and audio data

Claim 2

A decoder according to claim 1, further comprising: means (140) for detecting the header timing of each packet of the inputted group of packets, wherein updating an address used for storing the packet group in the first memory means is performed synchronously with an input timing of the packet header.

Claim 3

A decoder according to claim 1, further comprising: means (4) for generating a second clock signal having generally the same frequency as a first clock signal used as a time reference for compression coding; a counter (123) for counting the second clock signal: sampling means (124) for sampling the count of the counter synchronously with the header timing of each pocket of the inputted group of packets, the first memory means having an area for storing the count sampled by the sampling means at an address of the packet stored in the first memory means; and means (12) for controlling the frequency of the second clock signal generating means, by using a difference change between the stored count and a time stamp if the packet contains the time stamp of the first clock signal.

Claim 4

A decoder according to claim 2, further comprising: means (4) for generating a second clock signal having generally the same frequency as a first clock signal used as a time reference for compression coding; a counter (123) for counting the second clock signal: sampling means (124) for sampling the count of the counter synchronously with the header timing of each pocket of the inputted group of packets, the first memory means having an area for storing the count sampled by the sampling means at an address of the packet stored in the first memory means; and means (12) for controlling the frequency of the second clock signal generating means, by using a difference change between the stored count and a time stamp if the packet contains the time stamp of the first clock signal.

Claim 5

A decoder for compressed and multiplexed video and audio data for receiving a group of packets having a plurality of multiplexed packet sets each containing video data and associated audio data compressed by compression codes and packetized and outputting a set of video and audio signals, comprising: video decoder means (8) for decoding the compressed video data; audio decoder means (10) for decoding the compressed audio data; filter means (15) for filtering packets containing a set of particular video and audio data and a control packet containing attribute information of the group of packets; first memory means (71) for sequentially storing the filtered packets; processor means (12) for executing a process in accordance with a stored program, the process including sequentially reading a packet from the first memory means, supplying video and audio data to the video and audio decoder means, and supplying the attribute information of the set of particular video and audio data; second memory means (72) having a work area for at least the stored program; third memory means (73) for storing the attribute information contained in the control packet; and interface means (13) for transferring an external control signal to the processor means, the external control signal being used for filtering a set of video and audio data, wherein the first to third memory means are provided in the same memory element.

Claim 6

A decoder according to claim 1, further comprising: fourth memory means (74) provided in the same memory element as the first to third memory means, the fourth memory means being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoder means.

Claim 7

A decoder according to claim 2, further comprising: fourth memory means (74) provided in the same memory element as the first to third memory means, the fourth memory means being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoder means.

Claim 8

A decoder according to claim 3, further comprising: fourth memory means (74) provided in the same memory element as the first to third memory means, the fourth memory means being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoder means.

Claim 9

A decoder according to claim 4, further comprising: fourth memory means (74) provided in the same memory element as the first to third memory means, the fourth memory means being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoder means.

Claim 10

A decoder according to claim 5, further comprising: fourth memory means (74) provided in the same memory element as the first to third memory means, the fourth memory means being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoder means.

Claim 11

A decoder for compressed and multiplexed video and audio data for receiving a group of packets having a plurality of multiplexed packet sets each containing video data and associated audio data compressed by compression codes and packetized and outputting a set of video and audio signals, comprising: a video decoder (8) for decoding the compressed video data; an audio decoder (10) for decoding the compressed audio data; a first memory (71) for sequentially storing the group of packets; a processor (12) for executing a process in accordance with a stored program, the process including sequentially reading a packet from the first memory, filtering packets containing a set of particular video and audio data and a control packet containing attribute information of the group of packets, and supplying the particular video and audio data to the video and audio decoders; a second memory (72) having a work area for at least the stored program; a third memory (73) for storing the attribute information contained in the control packet; and an interface unit (13) for transferring an external control signal to the processor, the external control signal being used for filtering a set of video and audio data, wherein the first to third memories are provided in the same memory element.

Claim 12

A decoder according to claim 11, further comprising: a detector (140) for detecting the header timing of each packet of the inputted group of packets, wherein updating an address used for storing the group of packets in the first memory is performed synchronously with an input timing of the packet header.

Claim 13

A decoder according to claim 11, further comprising: a clock generator (4) for generating a second clock signal having generally the same frequency as a first clock signal used as a time reference for compression coding; a counter (123) for counting the second clock signal: a sampling unit (124) for sampling the count of the counter synchronously with the header timing of each pocket of the inputted group of packets, the first memory having an area for storing the count sampled by the sampling unit at an address of the packed stored in the first memory; and a unit (12) for controlling the frequency of the clock generator, by using a difference change between the stored count and a time stamp if the packet contains the time stamp of the first clock signal.

Claim 14

A decoder according to claim 12, further comprising: a clock generator (4) for generating a second clock signal having generally the same frequency as a first clock signal used as a time reference for compression coding; a counter (123) for counting the second clock signal: a sampling unit (124) for sampling the count of the counter synchronously with the header timing of each pocket of the inputted group of packets, the first memory having an area for storing the count sampled by the sampling unit at an address of the packed stored in the first memory; and a unit (12) for controlling the frequency of the clock generator, by using a difference change between the stored count and a time stamp if the packet contains the time stamp of the first clock signal.

Claim 15

A decoder for compressed and multiplexed video and audio data for receiving a group of packets having a plurality of multiplexed packet sets each containing video data and associated audio data compressed by compression codes and packetized and outputting a set of video and audio signals, comprising: a video decoder (8) for decoding the compressed video data; an audio decoder (10) for decoding the compressed audio data; a filter (15) for filtering packets containing a set of particular video and audio data and a control packet containing attribute information of the group of packets; a first memory (71) for sequentially storing the filtered packets; a processor (12) for executing a process in accordance with a stored program, the process including sequentially reading a packet from the first memory, supplying video and audio data to the video and audio decoders, and supplying the attribute information of the set of particular video and audio data; a second memory (72) having a work area for at least the stored program; a third memory (73) for storing the attribute information contained in the control packet; and an interface unit (13) for transferring an external control signal to the processor, the external control signal being used for filtering a set of video and audio data, wherein the first to third memories are provided in the same memory element.

Claim 16

A decoder according to claim 11, further comprising: a fourth memory (74) provided in the same memory element as the first to third memories, the fourth memory being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoders.

Claim 17

A decoder according to claim 12, further comprising: a fourth memory (74) provided in the same memory element as the first to third memories, the fourth memory being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoders.

Claim 18

A decoder according to claim 13, further comprising: a fourth memory (74) provided in the same memory element as the first to third memories, the fourth memory being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoders.

Claim 19

A decoder according to claim 14, further comprising: a fourth memory (74) provided in the same memory element as the first to third memories, the fourth memory being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoders.

Claim 20

A decoder according to claim 15, further comprising: a fourth memory (74) provided in the same memory element as the first to third memories, the fourth memory being used for compensating for a shift between a timing when the video signal is outputted and a timing when the audio signal associated with the video signal is outputted, the shift being caused by a process delay by one of the video and audio decoders.

Claim 21

A decoder for compressed and multiplexed application programs and data associated with the application programs for receiving a group of packets having a plurality of multiplexed packet sets each containing an application program and associated data compressed by compression codes and packetized and executing a desired application program, comprising: filter means (15) for filtering packets containing a set of particular application program and associated data and a control packet containing attribute information of the group of packets; first memory means (71) for sequentially storing the filtered packets; processor means (12) for executing a process in accordance with a stored program, the process including sequentially reading a packet from the first memory means, reading the set of particular application program and associated data from the read packets, and executing the set of particular application program and data; second memory means (72) having a work area for at least the particular application program; third memory means (73) for storing the attribute information contained in the control packet; and interface means (13) for transferring an external control signal to the processor means, the external control signal being used for filtering a desired set of application program and associated data, wherein the first to third memory means are provided in the same memory element.

Claim 22

A decoder according to claim 21, further comprising: display interface means (16) connected at least to the processor means for connecting an external monitor including display means to the decoder, wherein the processor means executes the application program, and supplies obtained graphics data to the external monitor to display the graphics data on the display means.

Claim 23

A decoder according to claim 22, wherein the external monitor includes a loudspeaker, the processor means executes the application program, and supplies obtained audio data to the external monitor to reproduce the audio data from the loudspeaker.

Claim 24

A decoder for compressed and multiplexed application programs and data associated with the application programs for receiving a group of packets having a plurality of multiplexed packet sets each containing an application program and associated data compressed by compression codes and packetized and executing a desired application program, comprising: a filter (15) for filtering packets containing a set of particular application program and associated data and a control packet containing attribute information of the group of packets; a first memory (71) for sequentially storing the filtered packets; a processor (12) for executing a process in accordance with a stored program, the process including sequentially reading a packet from the first memory, reading the set of particular application program and associated data from the read packets, and executing the set of particular application program and data; a second memory (72) having a work area for at least the particular application program; a third memory (73) for storing the attribute information contained in the control packet; and an interface unit (13) for transferring an external control signal to the processor, the external control signal being used for filtering a desired set of application program and associated data, wherein the first to third memories are provided in the same memory element.

Claim 25

A decoder according to claim 24, further comprising: a display interface unit (16) connected at least to the processor for connecting an external monitor including a display to the decoder, wherein the processor executes the application program, and supplies obtained graphics data to the external monitor to display the graphics data on the display.

Claim 26

A decoder according to claim 25, wherein the external monitor includes a loudspeaker, the processor executes the application program, and supplies obtained audio data to the external monitor to reproduce the audio data from the loudspeaker.

Claim 27

A receiver for encoded video and audio data, comprising: data selecting means (210 to 217) for selecting a set of packets and part or all of multiplexing information data and additional information data, from packets multiplexing a plurality of packet sets each having compression coded video data and audio data; bus access means (218) for supplying the selected set of packets, multiplexing information data, and additional information data to a bus; a microprocessor (204); a random access memory (203); a program memory (205); means (206) for processing the additional information data; means (207) for decoding the video data; and means (208) for decoding the audio data, wherein a set of packets, multiplexing information data, and additional information data respectively selected by the data selecting means are stored via the bus access means and the bus into the random access memory, data read from the random access memory is analyzed by the microprocessor, the video data, audio data, and additional information data are discriminated in accordance with the multiplexing information data, and via the bus the video data is supplied to the video data decoding means, the audio data is supplied to the audio data decoding means, the additional information data or processed additional information data is supplied to the additional information data processing means.

Claim 28

A receiver for encoded video and audio data according to claim 27, further comprising: filter means (213) for filtering clock information of a set of packets; and means (220) for generating a clock signal from the clock information, wherein the clock signal is supplied to the microprocessor, the video data decoding means, and the audio data decoding means.

Claim 29

A receiver for encoded video and audio data according to claim 27, further comprising: packet sync supply means (214) for supplying a packet sync signal of a set of packets to the microprocessor.

Claim 30

A receiver for encoded video and audio data according to claim 29, wherein the packet sync signal is inputted to the microprocessor as an interrupt signal, and in response to the interrupt signal data of one packet is stored in the random access memory.

Claim 31

A receiver for encoded video and audio data according to claim 27, further comprising: data storage media interface means (222) for sending a set of packets and multiplexing information data selected by the data selecting means to data storage media and sending a set of reproduced packets from the data storage media to the bus access means.

Claim 32

A receiver for encoded video and audio data according to claim 27, further comprising: a plurality of data selecting means, and data storage media interface means (222), wherein the data storage media interface means sends a set of packets and multiplexing information data selected by one of the data selecting means to data storage media and sending a group of reproduced packets from the data storage media to the bus access means.

Claim 33

A receiver for encoded video and audio data, comprising: a data selector (210 to 217) for selecting a set of packets and part or all of multiplexing information data and additional information data, from packets multiplexing a plurality of packet sets each having compression coded video data and audio data; a bus access unit (218) for supplying the selected set of packets, multiplexing information data, and additional information data to a bus; a microprocessor (204); a random access memory (203); a program memory (205); an additional information data processing unit (206) for processing the additional information data; a unit (207) for decoding the video data; and a unit (208) for decoding the audio data, wherein a set of packets, multiplexing information data, and additional information data respectively selected by the data selector are stored via the bus access unit and the bus into the random access memory, data read from the random access memory is analyzed by the microprocessor, the video data, audio data, and additional information data are discriminated in accordance with the multiplexing information data, and via the bus the video data is supplied to the video data decoding unit, the audio data is supplied to the audio data decoding unit, the additional information data or processed additional information data is supplied to the additional information data processing unit.

Claim 34

A receiver for encoded video and audio data according to claim 33, further comprising: a filter (213) for filtering clock information of a set of packets; and a clock generator (220) for generating a clock signal from the clock information, wherein the clock signal is supplied to the microprocessor, the video data decoding unit, and the audio data decoding unit.

Claim 35

A receiver for encoded video and audio data according to claim 33, further comprising: a packet sync supply unit for supplying a packet sync signal of a set of packets to the microcomputer.

Claim 36

A receiver for encoded video and audio data according to claim 35, wherein the packet sync signal is inputted to the microprocessor as an interrupt signal, and in response to the interrupt signal data of one packet is stored in the random access memory.

Claim 37

A receiver for encoded video and audio data according to claim 33, further comprising: a data storage media interface unit (222) for sending a set of packets and multiplexing information data selected by the data selector to data storage media and sending a set of reproduced packets from the data storage media to the bus access unit.

Claim 38

A receiver for encoded video and audio data according to claim 33, further comprising: a plurality of data selectors, and a data storage media interface unit (222), wherein the data storage media interface unit sends a set of packets and multiplexing information data selected by one of the data selectors to data storage media and sending a set of reproduced packets from the data storage media to the bus access unit.