EP0757318A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A router element for routing messages in a processing system
Assignee: Hewlett Packard Development Co LP
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Filing: 1996-06-06
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Granted: —
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Expires: 2016-06-06
Abstract
Abstract A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
Inventors
- 👤 John C. Krause
- 👤 David J. Garcia
- 👤 Robert W. Horst
- 👤 Geoffrey I. Iswandhi
- 👤 David Paul Sonnier
- 👤 William Joel Watson
- 👤 Linda Ellen Zalzala
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 06:10
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31727; G06; G06F; G06F1/00; G06F1/04; G06F1/12; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/16; G06F11/1604; G06F11/1629; G06F11/1633; G06F11/1641; G06F11/1645; G06F11/165; G06F11/1658; G06F11/1675; G06F11/1679; G06F11/1687; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/14; G06F12/1458; G06F12/1483; H; H04; H04L; H04L47/00; H04L47/10; H04L49/00; H04L49/90; H04L49/901; H04L49/9057; H04L69/00; H04L69/40; G01R31/3181; G01R31/3185; G01R31/318533; G06F11/004; G06F11/1008; G06F11/1044; G06F11/1666; G06F11/167; G06F11/1683; G06F11/1695; G06F11/20; G06F11/202; G06F11/2043; G06F11/2097; G06F11/22; G06F11/26; G06F11/273; G06F11/2736; G06F2201/00; G06F2201/845; H04L12/00; H04L12/54; H04L12/56
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
218 words
An input/output routing apparatus for communicating digital information between a plurality of processing system elements, the communicated information being in the form of a message packet transmitted by a one of the plurality of processing system elements to another of the processing system elements, the message packet containing data identifying as the destination the another one of the plurality of processing system elements, the input/output routing apparatus comprising: a plurality of port means each coupled to corresponding ones of the plurality of processing system elements, the port means including means bi-directionally transmitting and receiving message packets between the input/output routing apparatus and the first and second pluralities of processing system elements; routing means responsive to the data identifying the destination for selecting a one of the plurality of port means to which the another one of the plurality of processing elements is coupled for transmitting the message packet to the another processing system element; means including means for checking the message packet for errors, and for sending with the message packet to the another one of the plurality of processing elements indicia of the error; and means for sending with the message packet to the another one of the plurality of processing elements indicia of an error when an error is found to exist in the message packet.
Claim 2
Dependent Claim
46 words
The input/output routing apparatus of claim 1, the routing means including means for checking the message packet for errors, and for sending with the message packet to the another one of the plurality of processing elements indicia of the lack of error in the message packet.
Claim 3
Dependent Claim
60 words
The input/output routing apparatus of claim 1, wherein the message packet contains source data identifying the one of the plurality of processing system elements as a source of the message packet, and including circuit means responsive to the source data to check that the message packet was received at a port means coupled to the one of the processing elements.
Claim 4
Dependent Claim
59 words
The input/output routing means of claim 3, including means responsive to the circuit means for causing an indicia of error to be included in the information transmitted to the another one of the processing system elements, indicating that the message packet was not received at the port means coupled to the one of the plurality of processing system elements.
Claim 5
Dependent Claim
49 words
The input/output routing apparatus of claim 1, including means operating to receive the message packet at a one of the port means coupled to the one of the plurality of processing system elements, and for transmitting the message packet at two other of the plurality of port means simultaneously.
Claim 6
Dependent Claim
154 words
Routing apparatus for communicating digital information between a plurality of processing system elements, the digital information being in the form of message packets transmitted by a first of the plurality of processing system elements to a second of the processing system elements, the message packets including destination data identifying the second processing system element as the destination, the routing apparatus comprising: a plurality of ports each having an input for receiving message packets and an output for transmitting message packets; routing means coupled to the input and the output of each of the plurality of port means and responsive to the destination data of a message packet received at an input to communicate the message packet to the output of a one of the plurality of port means for transmitting the message packet; and port enable means for inhibiting a message packet received at a predetermined input from being transmitted from a predetermined output.
Claim 7
Dependent Claim
74 words
The routing apparatus of claim 6, wherein the routing means includes addressable storage means for storing a number of multi-bit entries each identifying a corresponding output, the addressable storage means being responsive to at least a portion of the destination data of the message for selecting a one of the number of multi-bit entries to identify the output of the one of the plurality of port means to which the message packet is communicated.
Claim 8
Dependent Claim
42 words
The routing apparatus of claim 6, the port enable means including, for each input, a register containing enable information identifying for such input predetermined outputs of the plurality of port means to which message packets received at such input cannot be communicated.
Claim 9
Dependent Claim
26 words
The routing apparatus of claim 8, wherein the register for each input includes a bit position corresponding to each output of the plurality of port means.
Claim 10
Dependent Claim
32 words
The routing apparatus of claim 9, wherein the bit position is set to a first digital stage to inhibit communication of the message packet to the output corresponding to the bit position.
Claim 11
Dependent Claim
32 words
The routing apparatus of claim 7, wherein the portion of the destination data defines a region of a computing system that contains at least one of the plurality of processing system elements.
Claim 12
Dependent Claim
22 words
The routing apparatus of claim 11, wherein another portion of the destination data identifies the one processing system element within the region.
Claim 13
Dependent Claim
76 words
The routing apparatus of claim 7, including register means containing a default multi-bit entry identifying the output of a one of the plurality of port means as a default output to which the message packet may be communicated, the routing means including means coupled to the register means and to the addressable storage means for selecting the default multi-bit entry instead of the one of the plurality of multi-bit entries when predetermined conditions are not met.
References Cited (Backward Citations)
No citation records indexed.
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