Device and method for the implementation of protocol functions of the ATM adaptation layer (AAL1) in a B-ISDN network

Claim 2

Device according to claim 1, characterized in that said information packets (ATM_DU) transiting on said first bus (Tx_AAL_DATA, Tx_DATA_CK) and on said second bus (Rx_AAL_DATA, Rx_DATA_CK) are 53 byte information packets consisting of a 48-byte information packet (AAL1_PDU) and of 5 bytes of header (H0, H1, ..., H4).

Claim 3

Device according to claim 2, characterized in that said 5 bytes of the header (H0, H1, ..., H4) of said information packets (ATM_DU) include information necessary to create, by the ATM protocol layer, correct identifier parameters of ATM cells destined to be formed starting from said information packets (ATM_DU).

Claim 4

Device according to claim 2, characterized in that said information packet of 48 bytes (AAL1_PDU) consists of a 47 byte payload(AAL1_SDU) and of an additional control byte (D0) containing control information of the ATM class 1 adaptation layer.

Claim 5

Device according to claim 4, characterized in that said additional control byte (D0) includes a sequence counter (Seq_COUNT) of information packets (AAL1_PDU) transmitted.

Claim 6

Device according to claim 4, characterized in that said additional control byte (D0) includes an indicator (CSI) of the convergence sublayer CS of the ATM adaptation layer (AAL).

Claim 7

Device according to claim 2, characterized in that the upstream portion (AAL1_u) for the adaptation of data coming from said serial interface (PCM) towards said parallel interface (AAb) includes: - a serial-parallel converter (SP_UNIT) connected (AAL_UNIT_DATA_BIT, TX_Ck_BIT) to said serial interface (PCM); - a service buffer (SERV_PDU_BUF) connected (TX_DATA) to said serial-parallel converter (SP_UNIT); - a writing control unit (WR_UNIT) connected (Addr_Wr) to said service buffer (SERV_PDU_BUF) for the control of writing operations inside said service buffer (SERV_PDU_BUF) and for the creation, inside said service buffer (SERV_PDU_BUF), of an information packet (AAL1_PDU); - an address comparator (ADDR_COMP_TX) connected (Tx_AAL_ADDR, Tx_ADDR_MASK, Tx_ADDR_Ck) to said parallel interface (AAb) to recognize the presence, on said parallel interface (AAb), a transmission control concerning the application process implemented by said user device connected to said serial interface (PCM); - a data reading control unit (RD_UNIT) connected (Addr_Rd) to said service buffer (SERV_PDU_BUF) to control reading operations from said service buffer (SERV_PDU_BUF), connected (ENABLE) to said address comparator (ADDR_COMP_TX) to start reading operations, connected (Tx_Data_En, Tx_Data_Start, Tx_Data_Mask) to said parallel interface (AAb) to send transmission control signals towards said ATM protocol layer; - means (WR_UNIT) to create said 5 bytes of the header (H0, ..., H4); - an output control unit (OUT_UNIT) connected (Buf_Out_0, Buf_Out_1) to said service buffer (SERV_PDU_BUF), connected (SAR_PDU_HEADER) to said means (WR_UNIT) to create the 5 bytes of the header (H0,..,H4), connected (ENABLE_HEADER) to said reading control unit (RD_UNIT), connected (ADDR_Bus) to said address comparator (ADDR_COMP_Tx) and connected (Tx_AAL_Data, Tx_Data_Ck) to said parallel interface (AAb), the address comparator (ADDR_COMP_Tx) sending a signal (ENABLE) to the reading control unit (RD_UNIT) controlling the transmission of the information packet of 48 bytes (AAL1_SDU) and of the 5-byte information packet (H0, ..., H4) towards the output control unit (OUT_UNIT) which sends an information packet for a total of 53 bytes (ATM_DU) to the parallel interface (AAb) with the ATM layer.

Claim 8

Device according to claim 7, characterized in that said service buffer (SERV_PDU_BUF) consists of two separate portions (BUF_0, BUF_1) essentially having the same capacity, so that reading and wiring operations from/to said service buffer (SERV_PDU_BUF) can be made at the same time.

Claim 9

Device according to claim 7, characterized in that it includes a coding block for the processing of data coming out from said serial parallel converter (SP_UNIT) before the storing inside said service buffer (SERV_PDU_BUF).

Claim 10

Device according to claim 7, characterized in that said address comparator (ADDR_COMP_Tx) of said upstream portion (AAL1_u) is connected (Tx_ADDR) to a microprocessor interface (mP_INT_UNIT_Tx) to set the address of said application process.

Claim 11

Device according to claim 7, characterized in that said information packet stored in said service buffer (SERV_PDU_BUF) of said upstream portion (AAL1_u) has 47 byte size (AAL1_SDU), that said writing control unit (WR_UNIT) of said upstream portion (AAL1_u) includes means to create an additional control byte (D0) containing control information of the ATM class 1 adaptation layer and a sequence indicator (Seq_COUNT) of information packets (ATM_SDU) transmitted, and that said output control unit (OUT_UNIT) includes means to add said additional control byte (D0) to said 47-byte information packet (AAL1_SDU) forming an information packet of 48 bytes in total (AAL1_PDU).

Claim 12

Device according to claim 11, characterized in that said writing control unit (WR_UNIT) includes a block (SRTS_Tx) for the creation of information (CSI) relevant to the source clock of the application and for the insertion of said information (CSI) inside said additional control byte (D0) of information packets (ATM_DU) transmitted, said information relevant to the application source clock being obtained from a service clock signal (fnX) and from an application clock signal (Tx_Ck_bit) received by said serial interface (PCM).

Claim 13

Device according to claim 12, characterized in that said block (SRTS_Tx) for the creation of information (CSI) relevant to the source clock of the service includes means (CLOCK_ELAB, RG_RTS, MUX_RTS, ADD_0_TO_EVEN) for the insertion of information (CSI) relevant to the source clock inside the additional control bytes (D0) of some particular information packets only (ATM_DU) among all information packets transmitted by said device (AAL1).

Claim 14

Device according to claim 2, characterized in that the downstream portion (AAL1_d) for the adaptation of data coming from said parallel interface (AAb) towards said serial interface (PCM) (AAL1_d) includes: - an input buffer (IN_BUF) connected (Rx_AAL_Data, Rx_Data_Ck) to said parallel interface (AAb) to store said information packets of 53 bytes (ATM_DU) coming from the ATM layer; - an address comparator (ADDR_COMP_Rx) connected (IN_RG, ENABLE_WR) to said input buffer (IN_BUF) to recognize the presence in said input buffer (IN_BUF), of an information packet concerning the application process implemented by said user device connected to said serial interface (PCM); - a service buffer (AAL_PDU_BUFFER) connected (DATA_OUT) to said input buffer (IN_BUF); - a parallel-serial converter (PS_UNIT) connected (DATA_IN) to said service buffer (AAL_PDU_BUFFER) and connected (AAL_Unit_Data) to said serial interface (PCM); - an error check unit (H_CRC) in said 5 header bytes (H0, ..., H4) of the information packet stored in said input buffer (IN_BUF) connected (DATA_OUT) to said input buffer (IN_BUF) and connected (H_MASK, ENABLE_CELL, H_CRC_Control) to said address comparator (ADDR_CMP_Rx); - a header processor (AAL_HDP) connected (CRC4_val) to said error check unit (H_CRC) and connected (LOST, EN_WR_RAM, WRX, L_WR_CNT) to a control unit (AAL_PDU_BUF_CU) of said service buffer (AAL_PDU_BUFFER) to check writing operations inside said service buffer, the address comparator (ADDR_COMP_Rx) being suitable to send a signal (ENABLE_WR) to the input buffer (IN_BUF) to store data coming from the parallel interface (AAb) and suitable to send an enabling signal (ENABLE_CELL) to the error check unit (H_CRC) in the 5-byte header (H0, ..., H4), the check unit (H_CRC) being suitable to send in its turn a signal (CRC4_val) to the header processor (AAL_HDP) to enable (LOST, EN_WR_RAM, WRX, L_WR_COUNT) the writing of data corresponding to the 48-byte payload (AAL1_PDU) of the information packet of 53 bytes (ATM_DU) contained in the input buffer (IN_BUF) in the service buffer (AAL_PDU_BUFFER) through said control unit (AAL_PDU_BUF_CU), said control unit controlling also the sending of said data towards the serial interface (PCM).

Claim 15

Device according to claim 14, characterized in that said input buffer (IN_BUF) of said downstream portion (AAL1_d) consists of two separate portions (IN_BUF_0, IN_BUF_1) having essentially equal capacity, so that reading and writing operations from/to said input buffer (IN_BUF) can be made at the same time.

Claim 16

Device according to claim 14, characterized in that said address comparator (ADDR_COMP_Rx) of said downstream portion (AAL1_u) is connected (Rx_ADDR) to a microprocessor interface (mP_INT_UNIT_Rx) to set the address of said application process.

Claim 17

Device according to claim 14, characterized in that said 53 byte information packet (ATM_DU) coming from the ATM layer includes an additional control byte (D0) containing control information characteristic of the ATM adaptation layer class 1 and a sequence counter (Seq_COUNT) of information packets (AAL1_PDU) transmitted and that said header processor (AAL_HDP) includes means to analyze the values of sequence counters (Seq_COUNT) present in information packets stored time by time in said input buffer (IN_BUF).

Claim 18

Device according to claim 17, characterized in that said header processor (AAL_HDP) of said downstream portion (AAL1_d) is connected (ERR_SYNCH) to a microprocessor interface (mP_INT_UNIT_Rx) to transmit, an exception signal (ERR_SYNCH), once the presence of information packets (AAL1_PDU) out of sequence is determined.

Claim 19

Device according to claim 17, characterized in that said additional control byte (D0) includes also parity and cyclic redundancy codes for the control of the presence and correction of errors possibly present in said byte (D0), and that said downstream portion (AAL1_d) of said device (AAL1) includes a unit (SNP_CRC) for the control and correction of errors present in said additional control byte (D0).

Claim 20

Device according to claim 19, characterized in that said unit (SNP_CRC) to check and correct errors present in said additional control byte (D0) is connected (ERR_CRC) to a microprocessor interface (mP_INT_UNIT_Rx) to transmit an exception signal, once the presence of errors in said additions control byte (D0) and the impossibility to correct said errors is determined.

Claim 21

Device according to claim 14, characterized in that inside said service buffer (AAL_PDU_BUFFER) a virtual buffer (VIRTUAL BUFFER) is created, whose capacity parameters vary according to the values assumed by the three parameters, indicating the minimum accepted filling value (Underflow Level) of said service buffer (AAL_PD_BUFFER), the mean estimated filling value (Middle Level) of said service buffer (AAL_PDU_BUFFER) and the maximum accepted filling value (Overflow Level) of said service buffer (AAL_PD_BUFFER), respectively.

Claim 22

Device according to claim 14, characterized in that said downstream portion (AAL1_d) includes a device (SCR_UNIT) for the recovery of the source transmission clock.

Claim 23

Device according to claim 22, characterized in that said additional control byte (D0) includes also information (CSI) relevant to the source clock of the application, that said device (SCR_UNIT) for the recovery of the source clock includes: - a recovery unit (SRTS_Rx) of said information (CSI) relevant to the source clock of the application supplying a signal RTS (ADD_M) indicating an estimate of data transmission frequency calculated on a watching time (T) equal to the arrival time of a number K of information packets (AAL1_PDU); - means (COUNT_WR, DIV_8) supplying a cell writing signal (Cell_WR_Div_8), homogeneous to said signal RTS (ADD_M), indicating the writing frequency of a frame consisting of a number K of said information packets (AAL1_PDU) inside said service buffer (AAL_PDU_BUFFER); - a multiplexer (MUX_ADAPT_RTS) supplying at output said signal RTS (ADD_M) or cell writing signal (CELL_WR_DIV_8) as a selection signal (ADAPT_RTS) varies; - a logic arithmetic unit (ALU) supplying a filling signal (FILL_LEVEL) indicating the deviation between the filling level (Actual Level) of said service buffer (AAL_PDU_BUFFER) and a pre-set value indicating the mean estimated occupation value (Middle Level); and - a digital PLL (D_PLL) tracking the frequency of the transmitter setting the frequency of the receiver (RD_CK_Bit) according to said signal RTS (ADD_M) or of said cell writing signal (CELL_WR_DIV_8) and of said filling signal (FILL_LEVEL).

Claim 24

Device according to claim 23, characterized in that said digital PLL (D_PLL) includes a digital phase comparator (DPD) performing an estimate (PH) of the difference between the transmitter estimated frequency (ADD_M, Cell_WR_Div_8) and the receiver frequency, received with a feedback loop.

Claim 25

Device according to claim 24, characterized in that said digital phase comparator (DPD) includes a multiplexer (MX) receiving on its selection input (MX_SEL) said signal carrying the estimated frequency of the transmitter (ADD_M o Cell_WR_Div_8) and supplying on its outputs (MX_OUT) the numeric value -1 or a numeric value equal to the number of bits contained in said number K of information packets (AAL1_PDU), being the outputs of said multiplexer connected to the inputs of an adder (ADD_RD_CK) timed on the basis of the receiver frequency (Rd_CK_Bit) and with reset input connected to a filling signal (FILL_LEVEL) generated by said logic arithmetic unit (ALU).

Claim 26

Device according to claim 23, characterized in that said digital PLL (D_PLL) includes a digital filter (FILTER), a control unit (VCO) and a divider (DIVIDER).

Claim 27

Device according to claim 23, characterized in that said (SRTS_Rx) recovery unit of said information relevant to the source clock includes a capture unit RST RTS (RTS_CAPT_UNIT) connected to a FIFO memory (RTS_FIFO) and to a clock reconstruction unit (SIRU).

Claim 28

Device according to claim 27, characterized in that said clock reconstruction unit (SIRU) is suitable to generate a signal (ADD_M) whose duration is related to the number of residual cycles (RTS) at the reference frequency (fnX) obtained from the network frequency of the reference period consisting of a pre-set number of information packets (AAL1_PDU) at the source service frequency, said signal being used by said digital PLL to reconstruct the source clock.

Claim 29

Device according to claim 23, characterized in that said logic arithmetic unit (ALU) supplies said filling signal (FILL_LEVEL) referred also to the width of a band included between two values indicating the minimum (Underflow Level) and maximum accepted value (Overflow Level) for occupation of said service buffer (AAL_PD_BUFFER).

Claim 30

Method for the synchronization between two devices operating at an ATM adaptation layer (AAL) in a B-ISDN network using two devices according to claim 2, characterized in that it includes the following phases for each one of said devices to be synchronized: - transmit, through a second device AAL (AAL1_A), information packets (SYNCH_A) with null information content, indicating a synchronization request towards a second device AAL (AAL1_B) with which said AAL transmitting device (AAL1_A) shall synchronize; - receive, through said second device AAL (AAL1_B), a given number of said information packets (SYNCH_A) indicating the synchronization request and obtain from said information packets synchronization information; - on the basis of said synchronization information, place said second AAL (AAL1_B) device in a synchronization condition; - transmit, through said first device AAL (AAL1_B), information packets (SYNCH_RECEIVER_B) with null information content indicating the occurred synchronization condition with said first device AAL (AAL1_A); - receive, through said first device AAL (AAL1_A), said information packets (SYNCH_RECEIVER_B) indicating the occurred synchronization condition of said second device AAL (AAL1_B); - recognize, through said first device AAL (AAL1_A), the occurred synchronization of said second AAL device and start the transmission of information packets (INF) having non null information content between said first device AAL (AAL1_A) and said second device AAL (AAL1_B).

Claim 31

Method according to claim 30, characterized in that the header (H0,...,H4) of said information packets (ATM_DU) includes information (I1.I0) suitable to identify the type of information packet (SYNCH, SYNCH_RECEIVER, INF) and that said information packets having null information content (SYNCH, SYNCH_RECEIVER) are transmitted by said first device towards ATM connections differing one from the other according to the variation of the information packet.