EP0762655A2
Expired / Lapsed
EP
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Host signal processing communication system that compensates for missed execution of signal maintenance procedures
Assignee: PCTel Inc
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Filing: 1996-09-05
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Granted: —
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Expires: 2016-09-05
Abstract
Abstract An HSP communications system contains a host computer which executes a software modem program and a device containing a circular buffer and a D/A converter. Typically, the host executes update routines in response to interrupts from the device and writes to the circular buffer digital samples representing amplitudes of an analog signal complying with a desired communication protocol. The samples pass through the circular buffer to the D/A converter which converts the samples into an analog communication signal. In environments such as multi-tasking systems, the host may occasionally skip interrupts and not provide new samples when required. In this case, the D/A converter reuses samples in the circular buffer to generate a maintenance signal. The maintenance signal typically does not convey correct data but is sufficient to maintain a communication link and prevent a remote device from disconnecting or entering a retrain mode. To provide a smoother maintenance signal, the circular buffer's size contains samples for an integral number of periods at the carrier and baud frequency of the desired protocol. Error correction and retransmission replace incorrect or lost data.
Inventors
- 👤 Han C. Yeh
- 👤 Peter C. Chen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 14:43
CPC Classifications
H; H04; H04M; H04M11/00; H04M11/06; H04L; H04L69/00; H04L69/40
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
69 words
A communication system comprising: a host computer; a circular buffer coupled to the host computer; means, in the host computer, for generating digital samples and writing the digital samples to the circular buffer, wherein the digital samples represent amplitudes of an analog communication signal; and a digital-to-analog converter coupled to the circular buffer, wherein the digital-to-analog converter converts digital samples from the circular buffer into an analog communication signal.
Claim 2
Dependent Claim
26 words
The system of claim 1, wherein the means for generating and writing comprises a routine executed by the host computer in response to an interrupt signal.
Claim 3
Dependent Claim
63 words
The system of claim 2, further comprising: a clock circuit which generates a clock signal that controls a rate at which the digital-to-analog converter receives digital samples for conversion; and an interrupt control circuit which generates the interrupt signal, wherein the interrupt signal has a frequency which depends on a frequency of the clock signal and on a size of the circular buffer.
Claim 4
Dependent Claim
133 words
The device of claim 1, wherein the circular buffer comprises: a memory; a first counter coupled to provide an address signal to the memory during a write operation, wherein the address signal provided by the first counter changes each time a digital sample is written to the memory; a second counter coupled to provide the address signal to the memory during a read operation, wherein the address signal provided by the second counter changes each time a digital sample is read from the memory; and a control circuit coupled to the first and second counters, wherein the control resets the first counter if the address signal provided by the first counter represents a wrap-around address and resets the second counter if the address signal provided by the second counter represents the wrap-around address.
Claim 5
Dependent Claim
25 words
The device of claim 4, further comprising a register coupled to the control circuit and the host computer, wherein the register stores the wrap-around address.
Claim 6
Dependent Claim
13 words
The device of claim 4, further comprising means for changing the wrap-around address.
Claim 7
Dependent Claim
48 words
The device of claim 1, wherein the digital-to-analog converter converts samples from the circular buffer at a fixed sampling frequency, and a carrier frequency of the analog communication signal is an integer multiple of the sampling frequency divided by a number of storage locations used in circular buffer.
Claim 8
Dependent Claim
34 words
The device of claim 7, wherein a baud frequency of the analog communication signal is an integer multiple of the sampling frequency divided by the number of storage locations used in the circular buffer.
Claim 9
Dependent Claim
48 words
The device of claim 1, wherein the digital-to-analog converter converts samples from the circular buffer at a fixed sampling frequency, and a baud frequency of the analog communication signal is an integer multiple of the sampling frequency divided by a number of storage locations used in circular buffer.
Claim 10
Dependent Claim
61 words
A communication device comprising: an interface circuit adapted for connection to a local bus of a computer system; a circular buffer coupled to receive and store digital samples from the interface circuit; and a digital-to-analog converter coupled to the circular buffer, wherein the digital-to-analog converter converts samples from the circular buffer into an analog signal for transmission on a communications line.
Claim 11
Dependent Claim
52 words
The device of claim 10, further comprising an interrupt control circuit which generates an interrupt signal having a first frequency, wherein a clock signal that determines a rate at which the digital-to-analog converter receives samples from the circular buffer has a second frequency which is an integer multiple of the first frequency.
Claim 12
Dependent Claim
134 words
The device of claim 10, wherein the circular buffer comprises: a memory; a first counter coupled to provide an address signal to the memory during a write, wherein the address signal provided by the first counter changes each time a digital sample is written to the memory; a second counter coupled to provide the address signal to the memory during a read, wherein the address signal provided by the second counter changes each time a digital sample is read form the memory; and a control circuit coupled to the first and second counters, wherein the control resets the first counter when the address signal provided by the first counter represents a wrap-around address and resets the second counter when the address signal provided by the second counter represents the wrap-around address the wrap-around address.
Claim 13
Dependent Claim
13 words
The device of claim 12, further comprising means for changing the wrap-around address.
Claim 14
Dependent Claim
17 words
The device of claim 10, wherein the interface circuit is adapted for connection to an ISA bus.
Claim 15
Dependent Claim
58 words
The device of claim 10, wherein: the analog signal is a communication signal having a carrier frequency; the digital-to-analog converter converts samples at a sampling frequency; and the circular buffer has a size such that the carrier frequency is an integer multiple of the sampling frequency divided by the number of storage locations used in the circular buffer.
Claim 16
Dependent Claim
43 words
The device of claim 15, wherein the size of the circular buffer is also such that a baud frequency of the analog signal is an integer multiple of the sampling frequency divided by the number of storage locations used in the circular buffer.
Claim 17
Dependent Claim
62 words
The device of claim 10, wherein: the analog signal is a communication signal having a baud frequency; the digital-to-analog converter converts samples at a rate indicated by a sampling frequency; and the circular buffer has a size such that the baud frequency is an integer multiple of the sampling frequency divided by the number of storage locations used in the circular buffer.
Claim 18
Independent Claim
64 words
A method for generating a communication signal, comprising: generating a series of digital samples which represent an analog signal in compliance with a communication protocol; writing the digital samples to a set of storage locations; converting the digital samples into analog voltages in the communication signal, wherein the digital samples are converted according to a circular ordering of the storage locations in the set.
Claim 19
Dependent Claim
60 words
The method of claim 18, wherein: writing the samples to the set of storage locations occurs in response to an interrupt; and in response to an interrupt for which new samples are not written to the set of storage locations, converting the digital samples comprises converting the digital samples twice before writing new samples to the set of storage locations.
Claim 20
Independent Claim
95 words
A method for generating a communications signal, comprising: executing a program in a computer system to generate a series of digital samples which represent an analog signal in compliance with a communications protocol; writing the digital samples to a buffer, in response to interrupts in the computer system; converting the digital samples into analog voltage levels of the communication signal; and in response to one or more of the interrupts for which writing digital samples to the buffer does not occur, maintaining the communication signal by repeating conversion of digital samples stored in the buffer.
Claim 21
Dependent Claim
67 words
The method of claim 20, wherein the buffer is partitioned into a first half and a second half, and writing digital samples to the buffer comprises filling the first half of the buffer with digital samples while converting samples from the second half of the buffer and filling the second half of the buffer with digital samples while converting samples from the first half of the buffer.
Claim 22
Dependent Claim
53 words
The method of claim 21, further comprising generating the interrupts in the computer system, wherein the interrupts separated by a time which is required to convert the samples in half of the buffer, wherein writing digital samples comprises filling one half of the buffer each time the computer system responds to an interrupt.
Claim 23
Dependent Claim
94 words
The method of claim 22, further comprising: ignoring a first interrupt so that no samples are written into the buffer in response to the first interrupt; generating a count indicating a number of interrupts which are ignored; in response to a second interrupt, determining from the count whether digital samples currently being converted are from the first or second half of the buffer; and filling the first half of the buffer with digital samples in response to the second interrupt signal, only if currently converting digital samples from the second half of the buffer.
References Cited (Backward Citations)
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