Cache memory

Claim 2

A method according to claim 1 including selectively controlling validity of one or more lines in the cache, invalidating one line of the cache, writing data including an address to said one line at the same time as an associate operation is carried out using the same address, and controlling re-validation of said one line in dependence on the result of the associate operation, thereby validating said line only if no cache hit is found.

Claim 3

A method according to claim 1 or claim 2 in which in response to a cache hit in one CAM line, data stored in that line of the data memory portion is modified by said write operation.

Claim 6

A method according to claim 5 in which in response to a cache hit in CAM line, data stored in that line of the data memory portion is modified by said write operation.

Claim 7

A method according to claim 6 in which said CAM is used to store address data relating to a plurality of branch instructions and said data memory portion is used to store for each branch instruction in the cache, a target address for the branch instruction together with a prediction of whether the branch will be taken when the instruction is executed by a processor, said write operation effecting a modification of at least one of said target address or prediction in the event of a cache hit during said write operation.

Claim 8

A method according to claim 7 in which said data memory portion also holds a prediction strength value in addition to said prediction, and said write operation is effective to modify said prediction strength value in the event of a cache hit during the write operation.

Claim 9

A cache memory comprising a content addressable memory (CAM) portion having a plurality of lines coupled to a respective line of a data memory portion, said CAM portion having an associate input for inputting data to effect an associate operation and a write input for inputting data to effect a write operation, said associate input being connected to input selection circuitry to select either write data or associate data for connection to said associate input whereby an associate operation may be effected in parallel with a write operation using common address data, said memory further comprising line validation circuitry operable in response to a result of an associate operation to prevent data related to said common address being held in more than one line of said cache.

Claim 10

A branch target buffer including a cache memory as claimed in claim 9, said CAM portion holding address data relating to a plurality of branch instructions and said data memory portion holding for each branch instruction in the cache, a target address for the branch instruction together with a prediction of whether the branch will be taken when the instruction is executed by a processor.

Claim 11

A branch target buffer according to claim 10 in which said cache includes data modification circuitry operable in response to a write operation to modify data stored for a branch instruction located by a cache hit during a write operation.

Claim 12

A branch target buffer according to claim 11 in which said data memory portion includes storage circuitry for storing a prediction strength value in addition to said prediction for any branch instruction held in said cache, and said storage circuitry is responsive to said data modification circuitry to modify said prediction strength value in response to a write operation relating to a branch instruction in said buffer.

Claim 13

A computer system comprising a memory for holding a plurality of instructions, a processor for executing a plurality of instructions sequentially and a branch target buffer according to any one of claims 10 to 12 for predicting a target address for a branch instruction fetched from said memory for execution by said processor.