EP0795828A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Dynamic set prediction method and apparatus for a multi-level cache system
Assignee: Sun Microsystems Inc
•
Filing: 1997-02-21
•
Granted: —
•
Expires: 2017-02-21
Abstract
Abstract A cache structure which provides set-prediction information for a separate, second-level cache is provided. In the event of a first-level cache miss, the second-level set-prediction information is used to select the set in an N-way off-chip set-associative cache. This allows a set-associative structure to be used in a second-level cache (on or off chip) without requiring a large number of traces and/or pins. Since set-prediction is used, the subsequent access time for a comparison to determine that the correct set was predicted is not in the critical timing path unless there is a mis-prediction or a miss in the second-level cache. Also, a cache memory can be partitioned into M sets, with M being chosen so that the set size is less than or equal to the page size, allowing a cache access before a TLB translation is done, further speeding the access.
Inventors
- 👤 Robert Yung
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 16:49
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F12/0864; G06F12/0893; G06F12/0897; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054; G06F2212/00; G06F2212/60; G06F2212/608; G06F2212/6082
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
64 words
A first cache memory system comprising: a plurality of entries; a plurality of tags, each tag corresponding to one of said entries; and a plurality of second set predictors, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in a second cache memory where a predicted next entry to be accessed is predicted to be located.
Claim 2
Dependent Claim
49 words
The memory system of claim 1 further comprising: a plurality of first set predictors, each first set predictor corresponding to one of said entries, each first set predictor identifying a set in said first cache memory where a predicted next entry to be accessed is predicted to be located.
Claim 3
Dependent Claim
14 words
The memory system of claim 1 wherein a plurality of said entries are data.
Claim 4
Dependent Claim
14 words
The memory system of claim 1 wherein a plurality of said entries are instructions.
Claim 5
Dependent Claim
19 words
The memory system of claim 1 wherein a plurality of said entries each include a plurality of data words.
Claim 6
Dependent Claim
18 words
The memory system of claim 1 wherein a plurality of said entries each include a plurality of instructions.
Claim 7
Dependent Claim
16 words
The memory system of claim 1 wherein said second cache memory is a level two cache.
Claim 8
Dependent Claim
16 words
The memory system of claim 1 wherein said second cache memory is an Nth level cache.
Claim 9
Dependent Claim
19 words
The memory system of claim 1 wherein said first cache memory is a first level cache in a microprocessor.
Claim 10
Dependent Claim
20 words
The memory system of claim 1 wherein said second cache memory is an Nth level cache external to said microprocessor.
Claim 11
Dependent Claim
26 words
The memory system of claim 10 further comprising a Nth level cache tag memory on said microprocessor for storing tags for said external Nth level cache.
Claim 12
Dependent Claim
32 words
The memory system of claim 1 wherein each logical set in said second cache memory has a size less than or equal to the size of a page of a memory space.
Claim 13
Dependent Claim
27 words
The memory system of claim 1 further comprising: a second cache latch for storing a one of said second set predictors corresponding to a last accessed entry.
Claim 14
Dependent Claim
29 words
The memory system of claim 1 further comprising: a previous address latch for storing a last address accessed, for use in updating a set predictor for a current address.
Claim 15
Dependent Claim
105 words
A first cache memory system comprising: a plurality of entries; a plurality of tags, each tag corresponding to one of said entries; a plurality of second set predictors, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in a second cache memory where a predicted next entry to be accessed is predicted to be located; and a plurality of first set predictors, each first set predictor corresponding to one of said entries, each first set predictor identifying a set in said first cache memory where a predicted next entry to be accessed is predicted to be located.
Claim 16
Dependent Claim
19 words
The memory system of claim 15 wherein said first cache memory is a first level cache in a microprocessor.
Claim 17
Dependent Claim
20 words
The memory system of claim 15 wherein said second cache memory is a second level cache external to said microprocessor.
Claim 18
Dependent Claim
31 words
The memory system of claim 15 wherein each set in said second cache memory has a size less than or equal to the size of a page of a memory space.
Claim 19
Dependent Claim
77 words
A cache memory system comprising: a plurality of entries; a plurality of tags, each tag corresponding to one of said entries; and a plurality of set predictors, each set predictor corresponding to one of said entries, each set predictor identifying a set in a cache memory where a predicted next entry to be accessed is predicted to be located; wherein each set has a size less than or equal to the size of a page of memory.
Claim 20
Dependent Claim
88 words
A computer system comprising: a system memory; a microprocessor including a level one cache memory; a level two cache memory coupled to said microprocessor; said level one cache memory including a plurality of entries, a plurality of tags, each tag corresponding to one of said entries, and a plurality of second set predictors, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in said level two cache where a predicted next entry to be accessed is predicted to be located.
Claim 21
Dependent Claim
44 words
A microprocessor integrated on a single semiconductor chip, comprising: a first level cache; an Nth level cache controller, including comparator logic configured to compare addresses to Nth level cache tags; an Nth level cache tag memory storing tags for an external Nth level cache.
Claim 22
Independent Claim
77 words
A method for improving the accessing of a second cache memory system comprising the steps of: storing a plurality of entries; storing a plurality of tags, each tag corresponding to one of said entries; and storing a plurality of second set predictors, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in a second cache memory where a predicted next entry to be accessed is predicted to be located.
Claim 23
Dependent Claim
52 words
The method of claim 22 further comprising the steps of: storing a plurality of first set predictors, each first set predictor corresponding to one of said entries, each first set predictor identifying a set in said first cache memory where a predicted next entry to be accessed is predicted to be located.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.