EP0840474A2
Expired / Lapsed
EP
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Reconfigurable transceiver for asymmetric communication systems
Assignee: Motorola Solutions Inc
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Filing: 1997-10-28
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Granted: —
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Expires: 2017-10-28
Abstract
Abstract A transceiver (5) for an asymmetric communication system such as asymmetric digital subscriber line (ADSL) includes a configuration register (71) defining operation at either a central office (CO) or a remote terminal (RT). The configuration register (71) includes a control bit (72) for selecting either CO or RT mode. The transceiver (5) includes a signal processing module (70) configured according to the state of the control bit (72). For example, a digital interface (70) converts transmit data into transmit symbols and converts received symbols into receive data. The digital interface (70) uses a large memory (158) as a buffer in the transmit path and a small memory (160) as a buffer in the receive path in CO mode. In RT mode, the digital interface (70) uses the small memory (160) in the transmit path and the large memory (158) in the receive path. The selective configuration allows a single integrated circuit to be used in both CO and RT equipment.
Inventors
- 👤 Jody Everett
- 👤 Michael R. May
- 👤 Carlos Greaves
- 👤 Mathew A. Rybicki
- 👤 Matthew A. Pendleton
- 👤 John M. Porter
- 👤 Terence L. Johnson
- 👤 Peter R. Molnar
- 👤 Howard E. Levin
- 👤 Jeffrey P. Gleason
- 👤 Robin Wiprud
- 👤 Sujit Sudhaman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 08:00
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/14; H04L5/143; H04L27/00; H04L27/0002; H04L27/26; H04L27/2601; H04L27/2626; H04L27/2647; H04Q; H04Q2213/00; H04Q2213/13034; H04Q2213/1305; H04Q2213/13103; H04Q2213/1319; H04Q2213/13199; H04Q2213/1332
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
284 words
A transceiver (5) for an asymmetric communication system, characterized by: a transmit port adapted for coupling to an asymmetrical communication link, said transmit port transmitting data at a first data rate; a receive port adapted for coupling to said asymmetrical communication link, said receive port receiving data at a second data rate; a signal processor (60, 62, 64, 66, 68, 70, 72, 75, 76, 78) having a data input terminal for receiving a digital transmit signal, a data output terminal for providing a digital receive signal, an input terminal coupled to said receive port, and an output terminal coupled to said transmit port, said signal processor (60, 62, 64, 66, 68, 70, 72, 75, 76, 78) converting said digital transmit signal into a digital representation of an analog transmit signal having a frequency content, and converting a digital representation of an analog receive signal into said digital receive signal according to a frequency content of said digital representation of the analog receive signal; said signal processor (60, 62, 64, 66, 68, 70, 72, 75, 76, 78) characterized by: control means (71) for determining whether said first data rate is a first predetermined data rate and said second data rate is a second predetermined data rate, or whether said first data rate is said second predetermined data rate and said second data rate is said first predetermined data rate; and a signal processing module having an input coupled to said control means (71) and operable in first and second modes in response to said control means being in a first logic state (CO) or a second logic state (RT), respectively, wherein said transceiver (5) is selectively operable at either end of said asymmetrical communication link.
Claim 2
Dependent Claim
51 words
The transceiver (5) of claim 1 wherein said signal processing module comprises a digital interface (70) which converts said digital transmit signal into a plurality of transmit symbols at said first data rate, and converts a plurality of receive symbols received at said second data rate into said digital receive signal.
Claim 3
Dependent Claim
115 words
The transceiver (5) of claim 2 wherein said digital interface (70) uses a first memory buffer for converting said digital transmit signal into said plurality of transmit symbols and uses a second memory buffer which is smaller than said first memory buffer for converting said plurality of receive symbols into said digital receive signal when said control means indicates said first logic state (CO), and wherein said digital interface (70) uses said second memory buffer for converting said digital transmit signal into said plurality of transmit symbols and uses said first memory buffer for converting said plurality of receive symbols into said digital receive signal when said control means indicates said second logic state (RT).
Claim 4
Dependent Claim
118 words
The transceiver (5) of claim 1 wherein said signal processing module comprises a circular echo synthesis (CES) module (74) which interpolates a transmit signal representation based on the digital representation of an analog transmit signal to provide a cancellation signal when said control means indicates said first logic state (CO), and which generates a second cancellation signal in response to said transmit signal representation and decimates said second cancellation signal to provide said cancellation signal when said control means indicates said second logic state (RT), wherein said signal processor (60, 62, 64, 66, 68, 70, 72, 75, 76, 78) subtracts said cancellation signal from a receive signal representation based on the digital representation of an analog receive signal.
Claim 5
Dependent Claim
115 words
The transceiver (5) of claim 1 wherein said signal processing module comprises a fast Fourier transform (FFT) module (73) which performs an inverse FFT on a first transmit signal representation based on the digital representation of an analog transmit signal to provide a second transmit signal representation based on the digital representation of an analog transmit signal when said control means indicates said first logic state (CO), and which performs an FFT on a first receive signal representation based on the digital representation of an analog receive signal to provide a second receive signal representation based on the digital representation of an analog receive signal when said control means indicates said second logic state (RT).
Claim 6
Dependent Claim
106 words
The transceiver (5) of claim 1 wherein said signal processing module comprises a filter, wherein when said control means indicates said first logic state (CO) said filter filters a first transmit signal representation based on the digital representation of an analog transmit signal to provide a second transmit signal representation based on the digital representation of an analog transmit signal, and wherein when control means indicates said second logic state (RT) said filter filters a first receive signal representation based on the digital representation of an analog transmit signal to provide a second transmit signal representation based on the digital representation of an analog transmit signal.
Claim 7
Dependent Claim
104 words
The transceiver (5) of claim 1 wherein said signal processing module comprises an analog front end module (78) characterized by: an interpolator having an input for receiving a first transmit signal representation based on the digital representation of an analog transmit signal, and an output; and an oversampled modulator having an input coupled to said output of said interpolator, and an output coupled to said transmit port, wherein when said control means indicates said first logic state (CO) said interpolator has a first predetermined order and wherein when said control means indicates said second logic state (RT) said interpolator has a second predetermined order.
Claim 8
Dependent Claim
262 words
A transceiver (5) for an asymmetric communication system, comprising: a transmit port adapted for coupling to an asymmetrical communication link, said transmit port transmitting data at a first data rate; a receive port adapted for coupling to said asymmetrical communication link, said receive port receiving data at a second data rate; an internal bus (62); a data processor (60) coupled to said internal bus (62) for accessing memory locations via said internal bus (62) in response to a program; a digital interface (70) coupled to said internal bus (62) which processes a digital transmit signal into a plurality of transmit symbols at said first data rate, and processes a plurality of receive symbols received at said second data rate into a digital receive signal; a plurality of signal processing peripherals (73, 74, 76) coupled to said internal bus (62), wherein said data processor in conjunction with said plurality of signal processing peripherals processes said plurality of transmit symbols into a digital representation of an analog transmit signal, and processes a digital representation of an analog receive signal into said plurality of receive symbols; and a control means (71) for indicating whether said first data rate is a first predetermined data rate and said second data rate is a second predetermined data rate, or whether said first data rate is said second predetermined data rate and said second data rate is said first predetermined data rate; said control bit further determining a mode of operation of at least one said digital interface (70) and said plurality of signal processing peripherals (73, 74, 76).
Claim 9
Dependent Claim
81 words
The transceiver (5) of claim 8 wherein said data processor (60) further characterized by: an analog front end module (78) having an input terminal coupled to said receive port, an output coupled to said transmit port, and a bi-directional terminal coupled to said internal bus, wherein said analog front end module (78) processes the digital representation of an analog transmit signal into an analog transmit signal, and processes an analog receive signal into the digital representation of the analog receive signal.
Claim 10
Dependent Claim
70 words
The transceiver (5) of claim 8 in which each of said plurality of signal processing peripherals (73, 74, 76) having a control means for indicating whether said first data rate is a first predetermined data rate and said second data rate is a second predetermined data rate, or whether said first data rate is said second predetermined data rate and said second data rate is said first predetermined data rate.
References Cited (Backward Citations)
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