Content addressable memory

Claim 2

The CAM of claim 1, wherein the logic means comprises NAND circuit means which provides logical outputs in response to the outputs from the match line chains in a respective row.

Claim 3

The CAM of claim 1, further comprising means for sensing the transitions of data signals on the chains.

Claim 4

The CAM of claim 3, wherein the polarity of data signal swing to signify a match is up or down.

Claim 5

The CAM of claim 1, wherein i=2 and a pair of match line chains are oriented in mirror images, such that their outputs face each other, facilitating the logic combination of the two partial match results from the two chains, by a logic means.

Claim 6

The CAM of claim 5, wherein the logic means comprises AND logic means and the word match lines, resulting from the ANDing of partial match results on the match chains, one word match line per word, are routed so as to convey the match result to the encoding means.

Claim 7

The CAM of claim 6, wherein the word match lines are selectively routed physically over the core cells in a metal layer above all other signals used in the core cell.

Claim 8

The CAM of claim 6, wherein the encoding means comprises a plurality of encoders.

Claim 9

The CAM of claim 6, wherein multiple words are placed adjacent to the encoding means, with multiple word match lines running over each core cell, allowing multiple word match lines to be routed per row.

Claim 10

The CAM of claim 9, wherein the word match lines are selectively routed over the core cells in a metal layer above all other signals used in the core cell.

Claim 11

The CAM of claim 6, wherein the partial match results are selectively routed above the core cell, to be combined in the AND logic means.

Claim 12

The CAM of claim 11, wherein the results from pairs of match line segments are first combined by a logical AND operation into a secondary partial result, the result then being routed above the core cell, to be combined in a final AND gate adjacent to the encoder.

Claim 13

The CAM of claim 1, wherein the core cell comprises a plurality of field effect transistors (FETs) for data storing operation, and further comprising logic level/precharging means for supplying a first binary logic level to one end of the chain and for precharging the match line chain to a second binary logic level in response to a clock signal.

Claim 14

The CAM of claim 13, wherein the logic level/precharging means comprises means for tying the one end of the chain directly to the a power supply of the first binary logic level.

Claim 15

The CAM of claim 13, wherein the logic level/precharging means comprises a first FET at the other end of the chain nearest match sense circuitry.

Claim 16

The CAM of claim 15, wherein the logic level/precharging means further comprises means for precharging the chain to the second binary logic level, commencing following the beginning of the clock cycle during which the search is to be performed, by the first FET.

Claim 17

The CAM of claim 15, wherein the logic level/precharging means further comprises means for precharging the chain to the second binary logic level, commencing following the completion of search operation, continuing during the non-searching quiescent state of the CAM, and ceasing prior to the initiation of the next search operation, by the first FET, the chain's FETs being in a conducting state during precharge, due to the high logic level on their gates.

Claim 18

The CAM of claim 13, wherein the logic level/precharging means comprises the first FET at one end of the chain and a second FET at the other end of the chain farthest from match sense circuitry.

Claim 19

The CAM of claim 18, wherein the logic level/precharging means comprises means for connecting the one end of the chain to a power supply of the first binary logic level, by a third FET which is made conducting when the first and second FET are non-conducting, the chain's FETs being in a conducting state during precharge, due to the high logic level on their gates.

Claim 20

The CAM of claim 18, wherein the second FET is conducting when the first FET is non-conducting.

Claim 21

The CAM of claim 13, wherein, the logic level/precharging means comprises logic level means and precharging means, the precharging means being for precharging means comprises means for precharging the chain to the second binary logic level, commencing following the completion of the search operation, continuing during the non-searching quiescent state of the CAM, and ceasing prior to the initiation of the next search operation, by a first FET at the end of the chain nearest match sense circuitry, the logic level means being for directly tying the one end of the chain to a power supply of the first binary logic level, the core cell in the chain at the extreme one end to the match sense circuitry comprising FETs identical to those of the other core cells in the chain, the compare data being applied at the opposite polarity during the quiescent precharge state, such that the chain's FET is the only such FET in the chain which is non-conducting in the quiescent precharge state.

Claim 22

The CAM of claim 13, wherein, the logic level/precharging means comprises logic level means and precharging means, the precharging means being for precharging the chain to the second binary logic level, commencing following the completion of the search operation, continuing during the non-searching quiescent state of the CAM, and ceasing prior to the initiation of the next search operation, by a first FET at the end of the chain nearest match sense circuitry, the logic level means being for directly tying the chain to a power supply of the first binary logic level, the core cell at a predetermined and constant location in the chain comprises FETs identical to those of the other core cells in the chain, the compare data being applied at the opposite polarity during the quiescent precharge state, such that the chain's FET is the only such FET in the chain which is non-conducting in the quiescent precharge state, thereby any charge sharing occurring during the search of the chain tending to make a mismatch appear somewhat like a match, but with the degree of the charge sharing understood and accounted for.

Claim 23

The CAM of claim 1, wherein the order of the bits in the chains, and among the chains making up each word, is intentionally and deterministically scrambled, in order to limit match line, or partial match result, transitions and power dissipation.

Claim 24

The CAM of claim 13, wherein the core cell comprises: first and second N-channel FETs and first and second P-channel FETs forming two cross-coupled inverters for storing differential data; third and fourth N-channel FETs coupled with the differential data nodes to differential bit lines, the FETs being gated by a word line, so as to provide access for read and write data operations; a fifth N-channel FET; sixth and seventh N-channel FETs, either of them being gated by the positive storage node and for connecting a positive comparison bit line to the gate of the fifth N-channel FET, the other being gated by the negative storage node and for connecting a negative comparison bit line to the gate of the fifth N-channel FET, the comparison bit lines being physically distinct from the bit lines employed for read and write access, the source and drain of the fifth N-channel FET being connected to those of neighbouring cells to form a chain of such FETs.

Claim 25

A dummy match line chain for use in a CAM comprising an array of data store cells coupled with bit lines, the dummy match line chain comprising CAM cells.

Claim 26

The match line chain of claim 25, wherein the CAM cell is a model CAM cell, which is guaranteed to match and has its chain FET conducting, the model CAM cell comprising: a combination of two N-channel FETs and two P-channel FETs forming two cross-coupled inverters, implementing static differential data storage; two additional N-channel FETs, connecting the static differential data nodes to differential bit lines, gated by a word line, for the purpose of providing access for read and write operations; two further N-channel FETs, one being gated by a positive comparison bit line, and connecting a positive comparison bit line to the gate of a third further N-channel FET, the other being gated by a negative comparison bit line, and connecting a negative comparison bit line to the gate of the same third further N-channel FET; comparison bit lines being physically distinct from the bit lines employed for read and write access; third further N-channel FET, its gate connected as described above, with source and drain connected to like transistors in neighbouring cells to form a chain of such devices.

Claim 27

The match line chain of claim 25, wherein the CAM cell is a model CAM cell, which is guaranteed to match when one of the comparison bit lines is in a logical high state, and has its chain FET conducting in that case, the model CAM cell comprising: two optional N-channel FETs, with drain and source unconnected, gated by a word line, for the purpose of providing model loading to the word line; a combination of an N-channel FET and a P-channel FET forming an inverter, inverting the logical state of a positive comparison bit line; a combination of an N-channel FET and a P-channel FET forming an inverter, inverting the logical state of a negative comparison bit line; two further N-channel FETs, one being gated by the inverted positive comparison bit line, and connecting the negative comparison bit line to the gate of a third further N-channel FET, the other being gated by the inverted negative comparison bit line, and connecting the positive comparison bit line to the gate of the same third further N-channel FET; third further N-channel FET, its gate connected as described above, with source and drain connected to like transistors in neighbouring cells (or to appropriate other circuits in the boundary cases) to form a chain of such devices.

Claim 28

The match line chain of claim 25, wherein the CAM cell is a model CAM cell, which is guaranteed to match and has its chain FET conducting, the model cell comprising: a pair of differential bit lines, selectively included, but electrically unconnected to the remainder of the core cell; a negative comparison bit line, selectively included, but electrically unconnected to the remainder of the core cell; two N-channel FETs, connecting the static differential storage nodes to: the positive supply voltage, in the case of the negative static storage node, and a floating source, in the case of the positive static storage node, gated by a word line; a first P-channel FET, it source connected to the positive supply voltage, and its gate and drain connected together to the negative static storage node, which is kept in a logical high state by the arrangement; a third N-channel FET, its source connected to the negative supply voltage, its gate connected to the negative static storage node, said node pulled high by the first P-channel FET, resulting in its conduction such that its drain, connected to the positive static storage node, is kept in a logical low state by the arrangement; a second P-channel FET, its source connected to the positive supply voltage, its gate connected to the positive static storage node, said node being kept in a logical low state by the third N-channel FET as described above, resulting in its conduction such that its drain, connected to the negative static storage node, is reinforced in its logical high state imposed by the first P-channel transistor, described above; a fourth N-channel FET, its source connected to the negative supply voltage, its gate connected to the positive static storage node, resulting in it being in a non-conducting state, and its drain electrically unconnected to any other node; two further N-channel FETs: the first gated by the positive static storage node, and connecting a positive comparison bit line to the gate of a third further N-channel FET, said device being in a non-conducting state due to the logical low state of its gate; the second gated by the negative static storage node, and connecting the positive supply voltage to the gate of the same third further N-channel FET, said device being in a conducting state due to the logical high state of its gate; any comparison bit line or lines present being physically distinct from any present bit line or lines employed for read and write access; third further N-channel FET, its gate connected as described above and in a high state, the FET being in a conducting state, with source and drain connected to like transistors in neighbouring cells to form a chain of such devices.

Claim 29

The match line chain of claim 28, wherein in the model CAM cell, either or both of the (i) positive supply voltage connection to the transistor gated by the word line and also connected to the negative static storage node, and the (ii) positive comparison bit line connection to the first further N-channel FET, may be replaced with a floating or unconnected node.

Claim 30

The match line chain of claim 28, wherein in the model CAM cell, all differential nodes are substituted by their corresponding complementary polarities of positive and negative for negative and positive, respectively.

Claim 31

The match line chain of claim 29, wherein in the model CAM cell, all differential nodes are substituted by their corresponding complementary polarities of positive and negative for negative and positive, respectively.

Claim 32

The match line chain of claim 1, further comprising a dummy chain for determining when precharge of all chains is complete, the dummy chains comprising as many dummy cells as the core cells of an actual storage chain, the dummy chain always conducting to model a match, responding to compare bit line transitions in the same way as a real chain with a match, the dummy chain comprising means for detecting when precharge is complete, at its end opposite precharge circuitry.

Claim 33

The CAM of claim 1, further comprising a dummy word for determining when sufficient time has elapsed for a match to complete, wherein the word is segmented into the same number of chains as an actual word of storage; each chain has the same number of cells as an actual storage chain, but composed of dummy core cells, instead of real core cells; each chain always conducts to model a match, and responding to compare bit line transitions in the same way as a real chain with a match.

Claim 34

The CAM of claim 1, further comprising a global data bus, connecting peripheral circuitry to the words of the CAM, wherein the bus joins all words and is used for search, read or write operations, supplying bi-directional data, and all drivers onto the bus are tri-statable.

Claim 35

A core cell comprises: first and second N-channel FETs and first and second P-channel FETs forming two cross-coupled inverters for storing differential data; third and fourth N-channel FETs coupled with the differential data nodes to differential bit lines, the FETs being gated by a word line, so as to provide access for read and write data operations; a fifth N-channel FET; sixth and seventh N-channel FETs, either of them being gated by the positive storage node and for connecting a positive comparison bit line to the gate of the fifth N-channel FET, the other being gated by the negative storage node and for connecting a negative comparison bit line to the gate of the fifth N-channel FET, the comparison bit lines being physically distinct from the bit lines employed for read and write access, the source and drain of the fifth N-channel FET being connected to those of neighbouring cells to form a chain of such FETs.