EP0908827A2
Expired / Lapsed
EP
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Memory interface device and memory address generation device
Assignee: Panasonic Holdings Corp
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Filing: 1998-10-02
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Granted: —
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Expires: 2018-10-02
Abstract
Abstract A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
Inventors
- 👤 Yoichiro Miki
- 👤 Masahiro Tani
- 👤 Kazuki Ninomiya
- 👤 Naoya Tokunaga
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 21:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/345; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1673; H; H04; H04N; H04N19/00; H04N19/42; H04N19/423; H04N19/60; H04N19/61
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
146 words
A memory interface device, comprising: an input buffer including a plurality of input
areas; an output buffer including a plurality of output
areas; and a control section for controlling the input
buffer, the output buffer and a single port memory,
wherein: the control section controls the input buffer and
the single port memory so as to transfer a signal stored
in one of the input areas of the input buffer to the
single port memory while storing an input signal in
another one of the input areas of the input buffer; and the control section controls the output buffer
and the single port memory so as to output as an output
signal a signal stored in one of the output areas of the
output buffer while transferring a signal stored in the
single port memory to another one of the output areas of
the output buffer.
Claim 2
Dependent Claim
55 words
A memory interface device according to claim 1,
further comprising a bus width conversion circuit for
converting an output bus width of the input buffer to an
input bus width of the single port memory, and converting
an output bus width of the single port memory to an input
bug width of the output buffer.
Claim 3
Dependent Claim
62 words
A memory interface device according to claim 1,
wherein the input buffer is divided along a bit line
direction and along a word line direction of the input
buffer into a plurality of input areas, and the output
buffer is divided along a bit line direction and along a
word line direction of the output buffer into a plurality
of output areas.
Claim 4
Dependent Claim
51 words
A memory interface device according to claim 1,
wherein: each of the input buffer and the output buffer
outputs to the control section a request signal for
accessing the single port memory; and the control section has an arbitration circuit
for prioritizing access request signals based on a
predetermined priority sequence.
Claim 5
Dependent Claim
25 words
A memory interface device according to claim 1,
further comprising a circuit for writing a signal from
the input buffer directly to the output buffer.
Claim 6
Dependent Claim
51 words
A memory address generation device for generating a
plurality of addresses for accessing a memory, the device
comprising: an address update section for updating N addresses
(where N is a natural number) at a predetermined
timing based on a predetermined relationship among the N
addresses, wherein the updated addresses are incremented.
Claim 7
Dependent Claim
47 words
A memory address generation device according to
claim 6, wherein: the predetermined relationship among the N
addresses is represented by K predetermined values (where
K is a natural number); and the address update section updates at least one
of the N addresses using the K predetermined values.
Claim 8
Dependent Claim
57 words
A memory address generation device according to
claim 7, wherein: the K predetermined values are offset values; and the address update section selectively updates
one of the N addresses to obtain a reference address, and
updates each remaining one of the N addresses through a
calculation based on the reference address and one of the
offset values.
Claim 9
Dependent Claim
42 words
A memory address generation device according to
claim 8, wherein the address update section updates the
one of the N addresses to be the reference address in one
direction and updates each remaining one of the N addresses
in an opposite direction.
Claim 10
Dependent Claim
46 words
A memory address generation device according to
claim 6, wherein: a first synchronous signal and a second synchronous
signal which have different frequencies are provided;
and the address update section updates the N addresses
by selectively using the first synchronous signal or
the second synchronous signal.
Claim 11
Dependent Claim
44 words
A memory address generation device according to
claim 6, wherein: the address update section logically divides a
memory address space into a plurality of areas; and the address update section generates an address
by independently incrementing an address pointer in each
of the areas.
Claim 12
Dependent Claim
102 words
A memory address generation device according to
claim 11, wherein: the memory address apace starts from a start
address and ends with an end address; the address update section logically divides the
memory address space by a boundary into a first area
including the start address and a second area including
the end address; the address update section calculates an address
using a logical address based on the start address either
in the first area or in the second area; end the address update section inverts the calculated
address for the second area, thereby providing an actual
address in the second area.
Claim 13
Dependent Claim
92 words
A memory address generation device according to
claim 12, wherein: M first synchronous system signals (where M is a
natural number) and K second synchronous system signals
which are not synchronized with the M first synchronous
signals are provided; the address update section provides a special
memory area in the memory address space for storing the
second synchronous system signals; and the address update section calculates a read
address of the second synchronous system signal based on
a write address of the second synchronous system signal
and the second synchronous system signal.
References Cited (Backward Citations)
No citation records indexed.
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