Logic circuit synthesizing system

Abstract

Abstract PURPOSE:To synthesize a logic circuit where the number of gates and the maximum delay time are reduced by providing a logic circuit synthesizing part, a delay analyzing part, and a critical block extracting part. CONSTITUTION:Specifications of a synchronous logic circuit given in a hardware description language in the register transfer level or with function block diagrams is inputted to a logic circuit synthesizing part 3, and this part 3 synthesizes a detailed logic circuit in accordance with synthesizing rules of function blocks stored in a synthesizing rule base 2 and outputs a net list 4 and a synthesizing rule list 5 applied to respective function blocks. A delay analyzing part 6 outputs an error path list 7 in case of the existence of maximum delay error. When maximum delay error is detected in the delay analyzing part 6, the synthesizing rule list 5 and the error path list 7 are inputted to a critical block extracting part 8, and this part 8 extracts a critical function block 9 on the error path and instructs the logic circuit synthesizing part 3 to perform synthesis again with resect to this function block 9. Thus, the logic circuit where the number of gates and the maximum delay time are reduced.

Inventors

• 👤 Hiroshi Ichiyanagi
• 👤 一柳　洋

Bibliographic Details