Semiconductor memory with three-dimensional structure

Abstract

Abstract PURPOSE:To improve the integration of a memory array by forming a three- dimensional structure in which memory arrays having no connection contact to a bit line for each memory are commonly used for a word line to be stacked as lower and upper layers. CONSTITUTION:Parallel N<+> type impurity diffused regions 2-5 are formed in a stripe state on a P<+> type silicon substrate 1, the regions 2, 4 are source regions, and the regions 3, 5 are drain regions. A word line 10 is formed in a direction perpendicular to the regions 2-5 on a gate oxide film 11 on the substrate 1, and memory cells M11,..., M1n are formed between the regions 2, 4 and 3, 5. A single crystalline silicon film 13 is formed through an insulating film 12 provided on the line 10, source regions 6, 8 and drain regions 7, 9 are formed in a direction perpendicular to a gate electrode in parallel with each other by impurity diffusion on the film 13, and upper layer memory cells M21-M2n are formed to the gate electrode. Thus, the integration density can be improved.

Inventors

• 👤 Toshibumi Asakawa
• 👤 浅川　俊文
• 👤 Hide Okubo
• 👤 大久保　秀

Bibliographic Details