Inter-multiprocessor data transferring system

Abstract

Abstract PURPOSE:To prevent the data transfer of higher priority and higher real time property from being spoiled by the transfer of the data of lower priority by making each processor interrupt the data transfer through a system bus, and arbitrating the right of using by the bus arbiter circuit of high priority. CONSTITUTION:The processor 11-L requests the right of using of a bus to a bus arbiter 31 through a high priority data transfer bus using right request/ permit signal line 22-N. When the arbiter 31 receives a request, it persists the interruption of a transmitting operation against a low priority transmission data buffer queue 111 in the course of the transmitting operation at that time by a control line 24, and persists the interruption of a receiving operation against a low priority reception data buffer queue 1N4 in the course of a receiving operation. Then, the processor 11-L sends transfer data in a high priority transmission data buffer queue 112 to a data transfer bus 21 through a transmission data multiplex circuit 113. Thus, the data transfer of higher priority and higher real time property can be prevented from being spoiled by the transfer of the data of lower priority.

Inventors

• 👤 Toshio Ishizuka
• 👤 石塚　利夫

Bibliographic Details