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JPS55166333A Expired / Lapsed JP ⏱️ 0.0 years remaining

Digital phase modulator

Assignee: NEC Corp
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Filing: 1979-06-12
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Granted: —
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Expires: 1999-06-12
📄 Original PDF 🌐 Google Patents

Abstract

Abstract PURPOSE:To obtain the satisfactory characteristics even in case the converting speed of the A/D converting circuit is low, by installing the interpolation circuit which assumes the value at the time excepting the moment when the input analog signal is sampled to the output side of the A/D converting circuit. CONSTITUTION:The modulated analog signal is converted into the digital value via A/D converting circuit 2 and then supplied to adder circuit 3 via interpolation circuit 12. On the other hand, the output of circuit 5 which sets the fixed value is added by add-up circuit 4 which gives addition with every clock cycle supplied from terminal 10, and then supplied to circuit 3. The output of circuit 3 is applied to memory circuit 6 to obtain the sampled phase modulation wave, and this output is converted into the analog quantity via D/A modulating circuit 7 to become the continuous signals in terms of the time by LPF8. Here the velocity of circuit 2 is slower than circuit 7 to cause the discountinuous phase modulation. To compensate this, the value is assumed at the time excepting the sampling point by circuit 12 and by means of the value at each sampling point.

Inventors

  • 👤 Yoshihiko Akaiwa

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 06:14
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0328; G06F1/0335

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References Cited (Backward Citations)

JPS5243308A Cited

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