Output device of plural speed encoder

Abstract

Abstract PURPOSE: To simply and highly accurately connect the speed bit data of a plural speed encoder by correcting the speed bit data of a first encoder with the upper two bits of the speed bit data of a second encoder. CONSTITUTION: The speed bit signals by a first encoder, in which bit data θ 1 are denoted at MSB whereas data θ 4 are denoted at LSB, are corrected on the basis of TableIby a logic correcting circuit 1, which is composed of an exclusive OR, NAND, AND gate, inverter and multiplexer, with the upper bits θ 4 and θ 5 of the speed bit signals, in which the data θ 4 ' by a second encoder subsequent to the first encoder are denoted at MSB, and are impressed upon an output register 3. On the other hand, the speed bit signals by the second encoder are delayed by a preset time in accordance with the chock pulses from a mono-stable multi-vibrator 2, to which the LSB of the bit signals are applied, and are stored in the register 3. Thus, the speed bit signals by the plural encoders are highly accurately connected in a simple manner without any fine adjustment of the plural encoders. As a result, the speed can be measured easily and highly accurately. COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Hiroshi Nagashima
• 👤 Takashi Saito
• 👤 Kiyousuke Hamatsu

Bibliographic Details