Differential non-linearity correction system of analogue digital converter

Abstract

Abstract PURPOSE: To make it possible to correct the differential non-linearity of an A/D converter in real time by dividing the error between each output channel CH width of the A/D converter and the correct width into upper and lower limit values and storing them in the ROM for every CH. CONSTITUTION: When analogue signals are inputted to A/D converter 1, digital signals are outputted, and upper and lower limit values are read out from ROM 2 where the error between the CH width of the CH number corresponding to this output and the correct width is divided into upper and lower limit values and is stored. Upper and lower limit values are inputted to digital comparator 4 for the upper limit value and digital comparator 5 for the lower limit value respectively. Meanwhile, random binary generator 3 gives always random signals to comparators and compares two signals just when read signals from ROM 2 are inputted to comparators and gives a 1 addition or subtraction command to operator 6 on a basis of outputs of comparators 4 and 5 when the random value is larger or smaller than the upper limit and the lower limit. As a result, the differential non-linearity of the high-speed A/D converter can be corrected in real time to obtain good-differential linearity data. COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Atsushi Yoshimura

Bibliographic Details