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JPS5589984A Expired / Lapsed JP ⏱️ 0.0 years remaining

Static memory cell

Assignee: Fujitsu Ltd
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Filing: 1978-12-28
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Granted: —
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Expires: 1998-12-28
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Abstract

Abstract PURPOSE:To enable low power consumption of static memory, by connecting the power saving circuit being the impedant enabling to flow a small current to the degree that the memory state of the memory cell can be kept at non-selection. CONSTITUTION:The power save circuit PD consists of MOSFETQ7, and it is connected between the power supply Vcc and the point A. Thus, at the chip non- selection when the chip selection signal CS is at L level, the impedance of Q7 is increased and the potential at the point A is lower than the power supply Vcc by the voltage drop of the transistor Q7. Accordingly, to the memory cell MEM, the difference voltage between the point A and GND lower than Vcc is fed, and current limit in response to the mutual conductance gm of the transistor Q7 is made, allowing to save the power consumption.

Inventors

  • 👤 Keizo Aoyama
  • 👤 Eiji Noguchi
  • 👤 Takahiko Yamauchi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 17:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419

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