Junction type field effect transistor

Abstract

Abstract PURPOSE:To obtain a high pressure tight JFET by a method wherein a P type gate is installed in an N type Si layer on an insulating substrate with a given interval and a N<+> layer is arranged at the both sides holding a gate layer and a channel between them, and further, coating with a gate insulating film, each electrode is installed. CONSTITUTION:Ion is applied into an N type Si layer 4 on an insulating substrate 3, and P layers 5, 6 are formed so as to face each other having a given interval and to be extending between the mutually facing surface 7 and 8 of the N layer 4. And further, N<+> layers 9, 10 are formed so as to face toward each other holding a channel part between the P layers 5 and 6 between them and to be extending between the surfaces 7 and 8. A gate electrode 15 is installed on the face 7 of the layer 4 by means of an SiO2 film 14 and it is coupled 16, 17 ohmic-ly with the layer 5, 6 and further, source, drain electrodes 18, 19 are formed on N<+> layers 9, 10. When a space between the N layer 9, 10 is properly selected considering the concentration of the layer 4, then, the pressure tightness between the source and the drain becomes sufficiently high, and when layers 4, 5, 6, 9, 10 are formed thinly, then, the short channel effect is reduced. Since no suspending capacity exists to and from the insulating substrate 3, a system of high speed response is obtained.

Inventors

• 👤 Kiyoshi Ariyoshi
• 👤 Masahiro Akitani

Bibliographic Details