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JPS574141A Expired / Lapsed JP ⏱️ 0.0 years remaining

Wiring structure in semiconductor device

Assignee: Sanyo Electric Co Ltd
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Filing: 1980-06-10
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Granted: —
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Expires: 2000-06-10
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Abstract

Abstract PURPOSE:To reduce a height difference in the layers and prevent a cutting of the upper layer wirings by a method wherein inter-layer insulative film of Si-gate MOS device is of two layers, a metal layer contacted with a substrate area is arranged between the layers, and the metal layer is connected to the upper layer wirings. CONSTITUTION:Gate metal 6 composed of gate film 5 and poly-Si or Mo is arranged on, for example, P type substrate 1 divided by oxidation film 2, the wiring 7 is arranged on the oxidation film 2, thereafter PSG film 20 is accumulated to about 1/2 of a required thickness as an inter-layer film. Hot heat treatment is applied to have a diffusion N type layers 3, 4 in a source drain area, then an opening is made in the film 20, and a contact metal for example Al is extended over the oxidation film 2 to be formed thereon. Then, the insulation film 23 is formed to show a thickness which is substantially the same as that of the film 20, a contact hole is formed in the film 23, Al wiring 25 in the upper layer is formed, and connected to the contact metal 22. Thus, it is possible to reduce a height difference between the contact areas, so that a cutting of Al wiring may be prevented and its reliability in operation may also be improved.

Inventors

  • 👤 Hirotetsu Yoshino

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 09:23
CPC Classifications
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