Master slice chip

Abstract

Abstract PURPOSE:To facilitate wiring between semiconductor elements by a method wherein the first buried wiring layers extending in the first direction and the second buried wiring layers having the different direction are provided in the wiring regions to be interposed between plural element regions of a master slice chip. CONSTITUTION:The first wiring block 5 consisting of the first under paths 3 extending in the first direction and the second wiring block 6 consisting of the second under paths 4 extending in the direction being different from the first direction are formed in the wiring regions 1b of the master slice chip 1 being provided with plural element regions 1a and the wiring regions 1b provided between the former, and the prescribed under paths are selected to connect between the elements. Accordingly degree of freedom in use of the under paths is enlarged, and delay time of signal can be regulated minutely.

Inventors

• 👤 Hideyuki Miyazawa

Bibliographic Details