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JPS58100545A Expired / Lapsed JP ⏱️ 0.0 years remaining

logic circuit

Assignee: Toshiba Corp
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Filing: 1981-12-11
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Granted: —
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Expires: 2001-12-11
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Abstract

Abstract PURPOSE:To attain high-speed logic operable with a single power supply, by arranging a plurality of switching transistors SWTRs of normally-on type FETs longitudinally and providing a current path consisting of diodes and resistors to a common source terminal from the gate of the SWTRs. CONSTITUTION:An NAND stage is arranged with two normally-on type FETs longitudinally, and when ''1'' is inputted to an input (a) and ''0'' is inputted to an input (b), one input (d) of the NAND is ''0'' and an FETQ23 turns off and an FETQ22 also turns off and ''1'' is given to the other input (c) via a shift diode D22. If a diode D41 does not exist, since the FETQ23 is turned off, this current does not flow to a common connecting point (A), the current flowing to a diode D31 is reduced and the potential at the point (A) is fluctuated. Thus, the diode D41 is provided, allowing to make the potential of the common connecting point constant even if the switches are arranged longitudinally.

Inventors

  • 👤 Shoichi Shimizu
  • 👤 庄一 清水

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-07 22:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443

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