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JPS58220293A Expired / Lapsed JP ⏱️ 0.0 years remaining

Storage device

Assignee: NEC Corp
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Filing: 1982-06-15
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Granted: —
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Expires: 2002-06-15
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Abstract

Abstract PURPOSE:To improve the integration degree of a storage device, by providing a gate circuit which can separate a writing data bit line from a reading data bit line and a control line of the gate circuit and then supplying both bit lines to a data processor which requests two different data. CONSTITUTION:A 3-transistor dynamic RAM consists of word lines 1 and 2, bit lines 3 and 4, writing/reading MOSFET5 and 6, a capacity 7, a reading MOSFET8 and an inverter 9. A gate 10 which can separate a reading data bit line from a writing data bit line and a control line 11 of the gate 10 are added to the dynamic RAM. The gate 10 conducts when the line 11 is set at ''1'' to ensure the function of an ordinary RAM and then becomes nonconductive when the line 11 is set at ''0'' to separate electrically the line 3 from the line 4. Then it is possible to give two different data to a data processor 12. As a result, the number of wirings is reduced and the integration degree of IC is increased.

Inventors

  • 👤 Katsuhiko Nakagawa
  • 👤 克彦 中川
  • 👤 Takao Kusano
  • 👤 隆夫 草野

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 23:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C7/00; G11C7/10; G11C7/1051; G11C7/1078

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