Complementary type insulating gate field effect semiconductor memory device

Abstract

Abstract PURPOSE:To simultaneously attain the reduction of the resistance of a word wire and the miniaturization of a cell, and enable the high speed operation of a CMOS memory and the reduction of a chip size, by forming at least one of a word wire and a power source wire of the same wiring layer. CONSTITUTION:A Vcc wire 2 is formed of a diffused layer wiring, and bit wires 1 and 1' are formed of Al wirings. The GND wire 5 and the word wire 6 are formed of Mo wirings (wirings applied to cross hatching) in a direction rectangular with the bit wire. Thus, the resistance of the word wire is reduced more than that of a poly Si wiring by one figure or more by forming the word wire of Mo wiring. Simultaneously, the number of Al wirings is reduced to four (two of bit wires and two of internal wirings), and thus the reduction of a cell area is allowed.

Inventors

• 👤 Isao Sasaki
• 👤 佐々木　勇男

Bibliographic Details