Mos-type logical circuit

Abstract

Abstract PURPOSE:To realize an MOS-type logical circuit having no excessive allowable voltage or operation, by constituting the circuit to change the relationship between the output signal and the input signal within the limit of not changing the logic, by changing the electric potential outputted from the electric potential generating means. CONSTITUTION:Since an MOS transistor (TR) QP2 is turned off when the output voltage VO of an electric potential generating means, whose output electric potential can be changed nonreversibly, is set to an electric potential VH of VDD, the circuit becomes irrespective of oprations of MOS TRs QP2 and QP3 and is driven by only TRs QP1 and QP2 consisting a C-MOS inverter. On the other hand, since the TR QP2 always holds ''ON'' condition when the voltage VO is set to the electric potential of the earthing electric potential VSS side and the TR QP3 also attains to ''ON'' condition when an input signal Vin is at low level, the electric current from the VDD to an output signal Vout terminal under this condition is flowed in two routes; one through the TR QP1 and the other through the TRs QP2 and QP3. Therefore, when the VO is set to the VL, the delay time in the rise time of the Vout becomes shorter when compared with the case where the VO is VH, and, additionally, the value of the input voltage which turns the inverter approaches the VDD.

Inventors

• 👤 Satoshi Konishi
• 👤 頴 小西

Bibliographic Details