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JPS5882344A Expired / Lapsed JP ⏱️ 0.0 years remaining

Interruption control system

Assignee: Usac Electronic Ind Co Ltd
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Filing: 1981-11-11
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Granted: —
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Expires: 2001-11-11
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Abstract

Abstract PURPOSE:To form an interruption vector table when an interruption processing routine is loaded, by writing an interruption processing routine address in an entry to the interruption vector table specified by an interruption factor number. CONSTITUTION:A prescribed area in a main storage device 1 is assigned for an interruption vector table 8, and each entry 7 to the table 8 is given a number in order. An initial program loader loads a program including an interruption processing routine from the device 1 to a main storage device 6, but a dictionary part 3 is looked up at this time; when an interruption vector item 5 is present, the processing routine address in the item 5 is stored in an entry 7 of the table specified by the interruption factor number in the item 5, thereby forming an interruption vector table.

Inventors

  • 👤 Masanobu Tsuji
  • 👤 辻 正信
  • 👤 Takahiro Maruyama
  • 👤 恭弘 丸山

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 08:42
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812

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