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JPS6015944A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Hitachi Ltd
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Filing: 1983-07-08
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Granted: —
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Expires: 2003-07-08
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Abstract

Abstract PURPOSE:To flatten a semiconductor device through an easy process, and to reduce wiring capacitance by reticulately forming a narrow insular region in an isolation region. CONSTITUTION:A collector buried layer 2 is formed on the surface of a Si substrate 1, a Si epitaxial layer 3 as an active section for a transistor is shaped on the layer 2, and the whole is thermally oxidized. Grooves 5 approximately vertical to Si are formed, and ions are implanted while using residual SiO2 films 4 as masks. The SiO2 films 4 are removed, a thin SiO2 film 7 is formed on the surfaces of the grooves through second thermal oxidation, and a SiO2 film 8 in thickness in the same extent as the depth of the grooves is deposited on the film 7. The SiO2 film 8 is etched to obtain a flat surface. The width b of the groove must be brought within approximately one and a half times as long as the depth of the groove. It is preferable that the width (a) of Si of island sections is brought to the size of one fifth or less of (b) in order to reduce wiring capacitance. Openings are bored to a passivation film 18, and a base electrode 19, an emitter electrode 30 and a collector electrode 21 are formed, thus completing the transistor.

Inventors

  • 👤 Yoichi Tamaoki
  • 👤 玉置 洋一
  • 👤 Tokuo Kure
  • 👤 久礼 得男
  • 👤 Takeo Shiba
  • 👤 健夫 芝

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 09:07
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17

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