Frequency synchronizing system

Abstract

Abstract PURPOSE:To attain transmission/reception of data in a frequency at the terminal of reception side by synchronizing a transmission clock signal of a transmitter to a frequency of a clock signal requested by the state of a reception buffer of a receiver. CONSTITUTION:After data from a transmission line 22 is received at a reception circuit 6R of a device 2 at the reception side, the data is stored in a buffer memory 7. An output circuit 9 outputs contents of the buffer memory 7 at a clock frequency 35 from an oscillator 15. The selection of clock frequencies 31, 32 of a device at the transmission side is performed by a deciding circuit 8 of the device 2 at the reception side. That is, a request signal RQ is outputted to a transmission circuit 6T depending on the number of data in the buffer memory 7 in the deciding circuit 8 and outputted to a transmission line 23 in the clock frequecy 34 from an oscillator 14. The request signal RQ from the transmission line 23 is received by a reception circuit 4R of the device 1 at the transmission side, the signal is fed to a frequency switching circuit 5, where the clock frequencies 31, 32 are switched.

Inventors

• 👤 Masahiro Matsuda
• 👤 正宏 松田
• 👤 Akira Takeyama
• 👤 明 竹山
• 👤 Takashi Tazaki
• 👤 田崎　堅志
• 👤 Satoshi Nojima
• 👤 聡 野島
• 👤 Mitsuhiro Azuma
• 👤 充宏 東

Bibliographic Details