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JPS60198780A Expired / Lapsed JP ⏱️ 0.0 years remaining

Mos transistor device

Assignee: Seiko Instruments Inc
•
Filing: 1984-03-21
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Granted: —
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Expires: 2004-03-21
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Abstract

Abstract PURPOSE:To keep the characteristic of high withstand voltage without being influenced by the gate voltage value by a method wherein the titled device is provided with a double-diffused layer of required conductivity which couples two regions forming an offset section. CONSTITUTION:The double-diffused layer 22 is provided between an N<+> type diffused layer 18 and a P<--> type substrate 12 and consists of the first N<-> type diffused layer 23 one end of which has been formed so as to reach the lower part of the thinner part 15a of a gate insulation film and of the second N type diffused layer 24 formed in the layer 23 so as to extend from the lower part of the part 15a to the inside of a layer 18. In the layer 23 its impurity profile is determined so that the impurity concentration C gently varies with the depth D from the surface of the substrate 12 and that the concentration C in the substrate surface (D=0) decomes relatively smaller. The layer 24 has the impurity profile that the concentration C in the substrate surface is relatively larger and that the concentration C rapidly decreases with the increase in depth D.

Inventors

  • 👤 Masaharu Ozaki
  • 👤 尾崎 正晴

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 20:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D62/13; H10D62/149; H10D62/151; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516

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