Semiconductor device

Abstract

Abstract PURPOSE:To suppress the generation of a latch-up phenomenon on a CMOS (complementary metal oxide semiconductor) by a method wherein a current amplification factor is lowered and the generation of a positive feed back is suppressed by increasing the impurity density of the base of a a parasitic bipolar transistor and by lowering the injection efficiency from an emitter, and the resistance entering in parallel between the emitter and the base is reduced, thereby enabling to prevent voltage drop even when a current flows said resistance part. CONSTITUTION:The circumferences of an n-channel, the n<+> region which is the source of a p-channel MOS transistor, and a p<+> region are surrounded by the conductive layers 23 and 28 of the conductive type reverse to that of the source, and this constitutes a structure wherein the same potential is given to the sources 4 and 7 and reverse conductive type layers 23 and 28 from the surface of a substrate. As a result, the current amplification factor of a parasitic bipolar transistor and the resistance entering between an emitter and a base in parallel is made smaller, and a trimming current is increased, because a latch-up is generated, thereby enabling to suppress the generation of a latch-up.

Inventors

• 👤 Yoshitaka Tadaki
• 👤 芳隆 只木
• 👤 Yoshio Sakai
• 👤 芳男 酒井

Bibliographic Details