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JPS604241A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: NEC Corp
•
Filing: 1983-06-22
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Granted: —
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Expires: 2003-06-22
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Abstract

Abstract PURPOSE:To contrive to reduce the noise due to parasitic capacitance in a semiconductor integrated circuit device havng the structure of multilayer wiring. CONSTITUTION:Wirings 4 and 5 intersect with each other over an insulation film 2 on a semiconductor substrate 1, and a protection film 6 is formed thereon. A wiring 7 is inserted between the wirings 4 and 5 via insulation film 8. This wiring 7 is constructed so as to cover the whole region of intersection between the wirings 4 and 5 and fixed to a substrate potential. Therefore, the formation of the wiring 7 by means of a metal such as Al having a sufficiently small wiring resistance or poly Si causes no noise due to the parasitic capacitance, because the wiring 7 has the effect of electrical shielding between the wirings 4 and 5 and does not transmits the variation of the potential of one of them to the other.

Inventors

  • 👤 Hiromasa Yamamoto
  • 👤 山本 裕将

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 07:07
CPC Classifications
—

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5255881A Cited
JPS53108391A Cited
JPS53130991A Cited

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