Pipeline control system

Abstract

Abstract PURPOSE:To shorten a processing time by opening the input gate of an accumulator in the precharge period of an internal data bus and holding all contents at a precharge level when an instruction for loading new data in a register is executed. CONSTITUTION:An OR circuit 21 which controls the input gate transistor (TR) 16 of the accumulator (AccA) 14 according to the result of OR among control signals phi1, phix.cont3, and phix.cont3' is provided to pipeline control which performs the parallel preprocessing of plural instructions. The phix.cont3' is held on from time (t4) when a timing signal phi2 turns on and gate TRs 131 and 132 turn on to precharge th internal data bus to time t7 when a timing signal phi1 turns off, and the output of a register 18 is written in the AccA14 at time t5. Consequently, one more stage of a pipeline is superposed to shorten an apparent processing time by one machine cycle.

Inventors

• 👤 Shinjiro Toyoda
• 👤 豊田　新次郎

Bibliographic Details