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JPS6147650A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor integrated circuit device

Assignee: Hitachi Ltd
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Filing: 1984-08-13
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Granted: —
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Expires: 2004-08-13
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Abstract

Abstract PURPOSE:To improve integration density of IC by forming fine grooves which form the element isolation region by self-alignment at the side portion of etching mask. CONSTITUTION:A silicon oxide film 2 is formed on a semiconductor substrate 1 consisting of n<--> type silicon single crystal and a first heat proof oxide mask forming layer 3 is formed thereon and first and second etching mask forming layers 4, 5, 6 are sequentially formed thereon. A second etching mask forming layer 6 at the upper part of region where an n type well region is provided is partly removed and a first etching mask 8 is formed by oxidizing the specified area of the remaining mask forming layer 6. Thereby, mask alignment error between the wall region and element isolation region can be prevented. Since the width of fine grooves which forms element isolation region can be reduced and therefore integration density of IC can be improved.

Inventors

  • 👤 Kazuyuki Tsukuni
  • 👤 和之 津国
  • 👤 Kazuo Nojiri
  • 👤 野尻 一男

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 20:28
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10

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